公开(公告)号：US06534396B1

公开(公告)日：2003-03-18

申请号：US09686107

申请日：2000-10-10

Applicant: Fu-Jier Fahn ,  Kuo-Wei Lin ,  James Chen ,  Eugene Cheu ,  Chien-Shian Peng ,  Gilbert Fan ,  Kenneth Lin

Inventor： Fu-Jier Fahn ,  Kuo-Wei Lin ,  James Chen ,  Eugene Cheu ,  Chien-Shian Peng ,  Gilbert Fan ,  Kenneth Lin

IPC: H01L214763

CPC classification number: H01L24/11 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76819 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00

Abstract: Within a method for forming a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a patterned conductor layer having a topographic variation at a periphery of the patterned conductor layer. There is then formed over the substrate and passivating the topographic variation at the periphery of the patterned conductor layer a planarizing passivation layer formed of a thermally reflowable material. There is then formed upon the planarizing passivation layer a dimensionally stabilizing layer. Finally, there is then thermally annealed the microelectronic fabrication to form from the planarizing passivation layer a thermally annealed planarizing passivation layer. By employing formed upon the planarizing passivation layer the dimensionally stabilizing layer, there is attenuated within the thermally annealed planarizing passivation layer replication of the topographic variation at the periphery of the patterned conductor layer.

Abstract translation: 在形成微电子制造的方法中，首先提供衬底。 然后在衬底上形成图案化导体层，该图案化导体层在图案化导体层的外围具有地形变化。 然后形成在衬底上并钝化图案化导体层的周边的地形变化，由可热再热材料形成的平坦化钝化层。 然后在平坦化钝化层上形成尺寸稳定层。 最后，然后将微电子制造热退火，从平坦化钝化层形成热退火的平坦化钝化层。 通过在平坦化钝化层上形成的尺寸稳定层，在图案化导体层的周边处的热退火的平坦化钝化层复制中的地形变化处被衰减。

公开(公告)号：US06977213B1

公开(公告)日：2005-12-20

申请号：US10928612

申请日：2004-08-27

Applicant: Yu-Ying Tsai ,  Shih-Ming Chen ,  Kuo-Wei Lin

Inventor： Yu-Ying Tsai ,  Shih-Ming Chen ,  Kuo-Wei Lin

IPC: H01L21/44 ,  H01L21/60 ,  H01L23/485

CPC classification number: H01L24/12 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13012 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Disclosed herein are a method of manufacturing a solder bump on a semiconductor device, a solder bump structure formed on a substrate, and an intermediate solder bump structure. In one embodiment, the method includes creating a bonding pad over a semiconductor substrate, and placing a mask layer over the substrate and the bonding pad. The method also includes forming an opening in the mask layer having a primary solder mold and at least one secondary solder mold joined with the primary mold, where the opening exposes a portion of the bonding pad. In this embodiment, the method further includes filling the primary solder mold and the at least one secondary solder mold with solder material to form corresponding primary and at least one secondary solder columns in electrical contact with the bonding pad. The method also includes removing the mask layer after the filling of the solder molds with the solder material. The method still further includes reflowing the solder material to form a primary solder bump from the solder material of the primary solder column and at least a portion of the solder material from the at least one secondary solder column through cohesion of the solder material from the at least one secondary solder column to the primary solder column when melted.

Abstract translation: 本文公开了一种在半导体器件上制造焊料凸块的方法，形成在基板上的焊料凸块结构和中间焊料凸块结构。 在一个实施例中，该方法包括在半导体衬底上形成接合焊盘，并将掩模层放置在衬底和焊盘上。 该方法还包括在掩模层中形成具有初级焊料模具的开口和与初级模具连接的至少一个次级焊接模具，其中开口暴露焊接区的一部分。 在该实施例中，该方法还包括用焊料材料填充主焊料模具和至少一个二次焊接模具，以形成与焊盘电接触的相应的初级和至少一个次级焊料柱。 该方法还包括在用焊料材料填充焊料模具之后去除掩模层。 该方法还包括回流焊料材料以从主焊料柱的焊料材料形成主要焊料凸点，并且通过焊料材料与焊料的内聚力从至少一个辅助焊料柱形成至少一部分焊料材料 当熔化时，至少一个辅助焊料柱到主焊料柱。

公开(公告)号：US20050258536A1

公开(公告)日：2005-11-24

申请号：US10851576

申请日：2004-05-21

Applicant: Kuo-Wei Lin ,  Hsaio-Ping Chang

Inventor： Kuo-Wei Lin ,  Hsaio-Ping Chang

IPC: H01L21/48 ,  H01L21/60 ,  H01L23/34 ,  H01L23/373 ,  H01L23/498

CPC classification number: H01L23/3735 ,  H01L21/4871 ,  H01L23/49816 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: An IC chip heat sink and method for dissipating heat from an integrated circuit (IC) chip, is disclosed. In a typical embodiment, the IC chip heat sink is fabricated by depositing a metal seed layer on the backside of a semiconductor wafer having multiple IC chips fabricated thereon. A photoresist layer is then deposited on the seed layer and patterned to define multiple photoresist openings. Multiple columns are formed on the seed layer by the electrochemical plating of a metal in the photoresist openings. Finally, the photoresist is stripped from the seed layer to define the multiple columns, which extend from the seed layer, and a network of heat sink channels between the columns. During functioning of the chip, heat is dissipated from the chip through the heat sink.

Abstract translation: 公开了一种用于从集成电路（IC）芯片散热的IC芯片散热器和方法。 在典型的实施例中，通过在其上制造多个IC芯片的半导体晶片的背面上沉积金属晶种层来制造IC芯片散热器。 然后将光致抗蚀剂层沉积在种子层上并图案化以限定多个光致抗蚀剂开口。 通过在光致抗蚀剂开口中的金属的电化学电镀，在种子层上形成多个柱。 最后，从种子层剥离光致抗蚀剂以限定从种子层延伸的多个柱和在柱之间的散热器通道网络。 在芯片运行期间，散热片从芯片散热通过散热片。

公开(公告)号：US06756184B2

公开(公告)日：2004-06-29

申请号：US09976067

申请日：2001-10-12

Applicant: Chiou-Shian Peng ,  Euegene Chu ,  Alex Fahn ,  Kenneth Lin ,  Gilbert Fane ,  James Chen ,  Kuo-Wei Lin

Inventor： Chiou-Shian Peng ,  Euegene Chu ,  Alex Fahn ,  Kenneth Lin ,  Gilbert Fane ,  James Chen ,  Kuo-Wei Lin

IPC: G03F700

CPC classification number: H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11502 ,  H01L2224/11849 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2224/11901 ,  H01L2224/1146

Abstract: A method of making electrically conductive bumps of improved height on a semiconductor device. The method includes steps of depositing an under bump metallurgy over a semiconductor device onto a contact pad; depositing and patterning a photoresist layer to provide an opening over the under bump metallurgy; depositing a first electrically conductive material into the opening in the photoresist layer; depositing a second electrically conductive material over the first electrically conductive material; removing the photoresist layer and the excess under bump metallurgy; applying a flux agent to the top surface of the second electrically conductive material; hard baking the semiconductor device to remove any oxide; dipping a portion of the semiconductor device in an electroless plating solution; removing the semiconductor device from the electroless plating solution; and reflowing the electrically conductive materials to provide a bump of improved height on the semiconductor device.

Abstract translation: 一种在半导体器件上制造改进的高度的导电凸块的方法。 该方法包括以下步骤：在半导体器件上沉积凸块下的金属到接触焊盘上; 沉积和图案化光致抗蚀剂层以在凸块下冶金上提供开口; 将第一导电材料沉积到光致抗蚀剂层的开口中; 在所述第一导电材料上沉积第二导电材料; 去除光致抗蚀剂层和过量的凸块下冶金; 将助熔剂施加到所述第二导电材料的顶表面; 硬烘烤半导体器件去除任何氧化物; 将半导体器件的一部分浸入化学镀溶液中; 从化学镀液中除去半导体器件; 并且回流所述导电材料以在所述半导体器件上提供改善高度的突起。

公开(公告)号：US06482669B1

公开(公告)日：2002-11-19

申请号：US09867379

申请日：2001-05-30

Applicant: Yang-Tung Fan ,  Chiou-Shian Peng ,  Cheng-Yu Chu ,  Shih-Jane Lin ,  Yen-Ming Chen ,  Fu-Jier Fan ,  Kuo-Wei Lin

Inventor： Yang-Tung Fan ,  Chiou-Shian Peng ,  Cheng-Yu Chu ,  Shih-Jane Lin ,  Yen-Ming Chen ,  Fu-Jier Fan ,  Kuo-Wei Lin

IPC: H01L2100

CPC classification number: H01L27/14685 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14645 ,  H01L31/02162 ,  H01L31/02327

Abstract: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon. A transparent encapsulant is deposited to planarize the color filter layer and completes the solid-state color image-forming device without conventional convex microlenses.

Abstract translation: 公开了一种有序的微电子制造顺序，其中滤色器通过直角沉积直接形成在CCD，CID或CMOS成像装置的光电检测器阵列上以形成凹入像素表面，并且覆盖有高透光率平面化膜 指定的折射率和物理性质，其优化光收集到光电二极管而不需要额外的常规微透镜。 光学平坦的顶表面用于封装和保护成像仪免受化学和热清洁处理损伤，最小化形成在非平面表面上的图像的像差或引起反射损失的形貌底层变化，并避免在切割和包装期间引起的残留颗粒夹杂物 。 通过在半导体衬底上光刻地构图光电二极管平面阵列来形成CCD成像器。 光电二极管阵列设置有金属遮光罩，钝化，并且在其上形成滤色器。 沉积透明密封剂以平坦化滤色器层并完成固态彩色图像形成装置，而不需要常规的凸起的微透镜。

公开(公告)号：US06372545B1

公开(公告)日：2002-04-16

申请号：US09814039

申请日：2001-03-22

Applicant: Fu-Jier Fan ,  Kuo-Wei Lin ,  Yen-Ming Chen ,  Cheng-Yu Chu ,  Shih-Jane Lin ,  Chiou-Shian Peng ,  Yang-Tung Fan

Inventor： Fu-Jier Fan ,  Kuo-Wei Lin ,  Yen-Ming Chen ,  Cheng-Yu Chu ,  Shih-Jane Lin ,  Chiou-Shian Peng ,  Yang-Tung Fan

IPC: H01L2144

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11901 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/19043 ,  H01L2924/00014

Abstract: A method for forming an under bump metal, comprising the following steps. A semiconductor structure is provided having an exposed I/O pad. A patterned passivation layer is formed over the semiconductor structure, the patterned passivation layer having an opening exposing a first portion of the I/O pad. A dry film resistor (DFR) layer is laminated, exposed and developed to form a patterned dry film resistor (DFR) layer over the patterned passivation layer. The patterned dry film resistor (DFR) layer having an opening exposing a second portion of the I/O pad. The patterned dry film resistor (DFR) layer opening having opposing side walls with a predetermined profile with an undercut. A metal layer is formed over the patterned dry film resistor (DFR) layer, the exposed third portion of the I/O pad, and over at least a portion of the opposing side walls of the patterned dry film resistor (DFR) layer opening. The patterned dry film resistor (DFR) layer is lifted off, along with the metal layer over patterned dry film resistor (DFR) layer and over at least the portion of the opposing side walls, leaving the metal layer over the exposed second portion of the I/O pad. The metal layer over the exposed second portion of the I/O pad being an under bump metal.

Abstract translation: 一种形成凸块下金属的方法，包括以下步骤。 提供具有暴露的I / O焊盘的半导体结构。 图案化的钝化层形成在半导体结构之上，图案化的钝化层具有暴露I / O焊盘的第一部分的开口。 将干膜电阻（DFR）层层压，曝光和显影以在图案化的钝化层上形成图案化的干膜电阻（DFR）层。 图案化的干膜电阻器（DFR）层具有露出I / O焊盘的第二部分的开口。 图案化的干膜电阻（DFR）层开口具有相对的侧壁，具有预定的具有底切的轮廓。 在图案化干膜电阻器（DFR）层，I / O焊盘的暴露的第三部分以及图案化干膜电阻器（DFR）层开口的相对侧壁的至少一部分之上形成金属层。 图案化的干膜电阻器（DFR）层与图案化的干膜电阻器（DFR）层上的金属层一起被提起并且在至少相对的侧壁的部分之上，使得金属层在暴露的第二部分 I / O焊盘。 I / O焊盘暴露的第二部分上的金属层是凸块下金属。

公开(公告)号：US07884471B2

公开(公告)日：2011-02-08

申请号：US11306015

申请日：2005-12-14

Applicant: Yu-Ying Tsai ,  Shih-Ming Chen ,  Kuo-Wei Lin

Inventor： Yu-Ying Tsai ,  Shih-Ming Chen ,  Kuo-Wei Lin

IPC: H01L29/40

CPC classification number: H01L24/12 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13012 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Disclosed herein are intermediate and solder bump structures. In one embodiment, a structure comprises a primary solder column comprising primary solder material and configured to electrically contact a bonding pad on a semiconductor substrate. The structure also comprises at least one secondary solder column comprising secondary solder material in electrical contact with the primary solder column, the at least one secondary column having a height and volume less than a height and volume of the primary solder column. In such structures, the primary solder column is further configured to form a primary solder bump comprising the primary solder material and at least a portion of the secondary solder material through cohesion from the at least one secondary solder column when the intermediate structure undergoes a reflow process.

Abstract translation: 本文公开了中间和焊料凸块结构。 在一个实施例中，结构包括主焊料柱，其包括主焊料材料并且被配置为电接触半导体衬底上的焊盘。 该结构还包括至少一个辅助焊料柱，其包括与主焊料柱电接触的次要焊料材料，所述至少一个第二柱具有小于主焊料柱的高度和体积的高度和体积。 在这种结构中，主焊料柱进一步构造成当中间结构经历回流工艺时，通过与至少一个次级焊料柱的内聚形成包括主焊料材料和至少一部分辅助焊料材料的主要焊料凸块 。

公开(公告)号：US07485906B2

公开(公告)日：2009-02-03

申请号：US11642225

申请日：2006-12-20

Applicant: Yang-Tung Fan ,  Chiou-Shian Peng ,  Cheng-Yu Chu ,  Shih-Jane Lin ,  Yen-Ming Chen ,  Fu-Jier Fan ,  Kuo-Wei Lin

Inventor： Yang-Tung Fan ,  Chiou-Shian Peng ,  Cheng-Yu Chu ,  Shih-Jane Lin ,  Yen-Ming Chen ,  Fu-Jier Fan ,  Kuo-Wei Lin

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L27/14685 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14645 ,  H01L31/02162 ,  H01L31/02327

Abstract: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon. A transparent encapsulant is deposited to planarize the color filter layer and completes the solid-state color image-forming device without conventional convex microlenses.

Abstract translation: 公开了一种有序的微电子制造顺序，其中滤色器通过直角沉积直接形成在CCD，CID或CMOS成像装置的光电检测器阵列上以形成凹入像素表面，并且覆盖有高透光率平面化膜 指定的折射率和物理性质，其优化光收集到光电二极管而不需要额外的常规微透镜。 光学平坦的顶表面用于封装和保护成像器免受化学和热清洁处理损伤，最小化形成的底层变化，其将形成在非平面表面上的图像的像差或引起反射损失，并且消除在切割期间引起的残留颗粒夹杂物， 打包。 通过在半导体衬底上光刻地构图光电二极管平面阵列来形成CCD成像器。 光电二极管阵列设置有金属遮光罩，钝化，并且在其上形成滤色器。 沉积透明密封剂以平坦化滤色器层并完成固态彩色图像形成装置，而不需要常规的凸起的微透镜。

公开(公告)号：US20080013605A1

公开(公告)日：2008-01-17

申请号：US11484630

申请日：2006-07-12

Applicant: Kuo-Wei Lin

Inventor： Kuo-Wei Lin

IPC: H04B1/00

CPC classification number: G01S19/30

Abstract: A method of GPS bit synchronization is disclosed. The method includes the steps of a) receiving plural serial C/A Codes, wherein a data bit is formed by m C/A Codes; b) sequentially providing a bin number ranged from 0 to m−1 to the plural C/A Codes; c) setting a sampling value k; d) sequentially determining adjacent two C/A Codes, C/A Code nk and C/A Code (n+1)k, wherein n={0, 1, 2, 3, . . . }, and calculating a sign change aggregate value of each bin number ranged from 0 to m−1; e) repeating step d) till there are k bin numbers having the sign change aggregate value equal to or greater than a first threshold, and summing the k bin numbers for obtaining a lookup value; and f) acquiring a bit boundary of the data bit according to the lookup value in the plural serial C/A Codes.

Abstract translation: 公开了一种GPS位同步的方法。 该方法包括以下步骤：a）接收多个串行C / A码，其中数据比特由m C / A码形成; b）顺序地提供从0到m-1到多个C / A码的箱号; c）设置采样值k; d）依次确定相邻的两个C / A码，C / A码nk和C / A码（n + 1）k，其中n = {0,1,2,3。 。 。 }，并计算每个仓号的符号变化汇总值，范围为0到m-1; e）重复步骤d），直到具有等于或大于第一阈值的符号变化聚合值的k个bin号，并且将k个bin数相加以获得查找值; 以及f）根据多个串行C / A码中的查找值来获取数据比特的比特边界。

公开(公告)号：US07119002B2

公开(公告)日：2006-10-10

申请号：US11012032

申请日：2004-12-14

Applicant: Kuo-Wei Lin

Inventor： Kuo-Wei Lin

IPC: H01L21/44

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/30107 ,  H01L2224/13099 ,  H01L2924/00014

Abstract: It is an object of the present invention to provide a method for solder bump formation using a combination of eutectic and high lead solders. The present invention provides a method for improving a solder bump composition for a flip chip.

Abstract translation: 本发明的目的是提供一种使用共晶和高铅焊料组合的焊料凸块形成方法。 本发明提供了一种用于改进倒装芯片的焊料凸块组合物的方法。