公开(公告)号：US10892250B2

公开(公告)日：2021-01-12

申请号：US16229562

申请日：2018-12-21

Applicant: Powertech Technology Inc.

Inventor： Ming-Chih Chen ,  Hung-Hsin Hsu ,  Yuan-Fu Lan ,  Hsien-Wen Hsu

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/552 ,  H01L23/373 ,  H01L23/00 ,  H01L21/56

Abstract: A stacked package structure has a metal casing, a stacked chipset, an encapsulation and a redistribution layer. The stacked chipset is adhered in the metal casing. The encapsulation is formed in the metal casing to encapsulate the stacked chip set, but a plurality of surfaces of the metal pads are exposed through the encapsulation. The redistribution layer is further formed on the encapsulation and electrically connects to the metal pads of the stacked chipset. Therefore, the stacked package structure includes the metal casing, so an efficiency of heat dissipation and structural strength are increased.

公开(公告)号：US20200381812A1

公开(公告)日：2020-12-03

申请号：US16554644

申请日：2019-08-29

Applicant: Powertech Technology Inc.

Inventor： Yun-Hsin Yeh ,  Hung-Hsin Hsu

IPC: H01Q1/38 ,  H01L21/56 ,  H01L23/31 ,  H01L23/66 ,  H01Q1/40

Abstract: An integrated antenna package structure including a circuit board, a chip, an encapsulant and an antenna is provided. The chip is disposed on and electrically connected to the circuit board. The encapsulant encapsulates the chip. The encapsulant has a first surface and a second surface, wherein the normal vector of the first surface is different from the normal vector of the second surface. The antenna is disposed on the first surface and the second surface of the encapsulant. A manufacturing method of an integrated antenna package structure is also provided.

公开(公告)号：US20200335456A1

公开(公告)日：2020-10-22

申请号：US16384940

申请日：2019-04-16

Applicant: Powertech Technology Inc.

Inventor： Wen-Jeng Fan

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package including a semiconductor chip, a conductive element disposed adjacent to the semiconductor chip, an insulating encapsulation covering the semiconductor chip and the conductive element, a redistribution structure disposed on the semiconductor chip and the conductive element, and a first buffer layer disposed between the redistribution structure and the insulating encapsulation is provided. The semiconductor chip is electrically coupled to the conductive element through the redistribution structure. The first buffer layer covers the semiconductor chip and the conductive element. A manufacturing method of a semiconductor package is also provided.

公开(公告)号：US20200273829A1

公开(公告)日：2020-08-27

申请号：US16521596

申请日：2019-07-25

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu ,  Shang-Yu Chang Chien ,  Nan-Chun Lin

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/522 ,  H01L21/56 ,  H01L21/768

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes first dies, an insulating encapsulation laterally encapsulating the first dies, a second die disposed over the portion of the insulating encapsulation and at least partially overlapping the first dies, and a redistribution structure disposed on the insulating encapsulation and electrically connected to the first dies and the second die. A second active surface of the second die faces toward first active surfaces of the first dies. The redistribution structure includes a first conductive via disposed proximal to the first dies, and a second conductive via disposed proximal to the second die. The first and second conductive vias are electrically coupled and disposed in a region of the redistribution structure between the second die and one of the first dies. The first conductive via is staggered from the second conductive via by a lateral offset.

公开(公告)号：US10756065B2

公开(公告)日：2020-08-25

申请号：US16741749

申请日：2020-01-14

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00 ,  H01L23/31

Abstract: A method of fabricating a package structure including at least the following steps is provided. A carrier is provided. A first package is formed on the carrier. The first package is formed by at least the following steps. A first redistribution layer is formed on the carrier, wherein the first redistribution layer has a first surface and a second surface opposite to the first surface. A semiconductor die is bonded on the first surface of the first redistribution layer. The semiconductor die is electrically connected to the first redistribution layer through a plurality of conductive wires. An insulating material is formed to encapsulate the semiconductor die and the plurality of conductive wires. A thinning process is performed to obtain an insulating encapsulant by reducing a thickness of the insulating material until a portion of each of the conductive wires is removed to form a plurality of conductive wire segments, wherein the semiconductor die is electrically insulated from the first redistribution layer after the thinning process. A second redistribution layer is formed on a top surface of the insulating encapsulant, and over the semiconductor die. The second redistribution layer is electrically connected to the first redistribution layer and to the semiconductor die by the plurality of conductive wire segments.

公开(公告)号：US20200243449A1

公开(公告)日：2020-07-30

申请号：US16261566

申请日：2019-01-30

Applicant: Powertech Technology Inc.

Inventor： Chia-Wei Chiang ,  Li-Chih Fang ,  Wen-Jeng Fan

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A package structure includes a redistribution structure, a bridge die, a plurality of conductive pillars, at least two dies, and an insulating encapsulant. The bridge die provides an electrical connection between the at least two dies. The conductive pillars provide an electrical connection between the at least two dies and the redistribution structure. The insulating encapsulant is disposed on the redistribution structure, encapsulates the bridge die and the conductive pillars, and covers each of the at least two dies. The bridge die of the package structure may be used to route signals between the at least two dies, allowing for a higher density of interconnecting routes between the at least two dies.

公开(公告)号：US20200091126A1

公开(公告)日：2020-03-19

申请号：US16687713

申请日：2019-11-19

Applicant: Powertech Technology Inc.

Inventor： Nan-Chun Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien ,  Wen-Hsiung Chang

IPC: H01L25/16 ,  H01L23/48 ,  H01L23/498 ,  H01L21/768 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package including a plurality of first chips, a plurality of through silicon vias, a least one insulator, a first circuit structure and a first encapsulant is provided. The first chip electrically connected to the through silicon vias includes a sensing area on a first active surface, a first back surface and a plurality of through holes extending from the first back surface towards the first active surface. The insulator is disposed on the first active surfaces of the first chips. The first circuit structure disposed on the first back surfaces of the first chips and electrically connected to the through silicon vias. The first encapsulant, laterally encapsulating the first chips.

公开(公告)号：US10522512B2

公开(公告)日：2019-12-31

申请号：US15968769

申请日：2018-05-02

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/66 ,  H01L23/538 ,  G01R31/28

Abstract: A semiconductor package including an ultra-thin redistribution structure, a semiconductor die, a first insulating encapsulant, a semiconductor chip stack, and a second insulating encapsulant is provided. The semiconductor die is disposed on and electrically coupled to the ultra-thin redistribution structure. The first insulating encapsulant is disposed on the ultra-thin redistribution structure and encapsulates the semiconductor die. The semiconductor chip stack is disposed on the first insulating encapsulant and electrically coupled to the ultra-thin redistribution structure. The second insulating encapsulant is disposed on the ultra-thin redistribution structure and encapsulates the semiconductor chip stack and the first insulating encapsulant. A manufacturing method of a semiconductor package is also provided.

公开(公告)号：US20190341369A1

公开(公告)日：2019-11-07

申请号：US15968769

申请日：2018-05-02

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/66 ,  H01L23/538 ,  G01R31/28

Abstract: A semiconductor package including an ultra-thin redistribution structure, a semiconductor die, a first insulating encapsulant, a semiconductor chip stack, and a second insulating encapsulant is provided. The semiconductor die is disposed on and electrically coupled to the ultra-thin redistribution structure. The first insulating encapsulant is disposed on the ultra-thin redistribution structure and encapsulates the semiconductor die. The semiconductor chip stack is disposed on the first insulating encapsulant and electrically coupled to the ultra-thin redistribution structure. The second insulating encapsulant is disposed on the ultra-thin redistribution structure and encapsulates the semiconductor chip stack and the first insulating encapsulant. A manufacturing method of a semiconductor package is also provided.

公开(公告)号：US10431549B2

公开(公告)日：2019-10-01

申请号：US15867670

申请日：2018-01-10

Applicant: Powertech Technology Inc.

Inventor： Chien-Wen Huang ,  Chia-Wei Chiang ,  Wen-Jeng Fan ,  Li-Chih Fang

IPC: H01L23/495 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L25/10

Abstract: A semiconductor package including a stacked-die structure, a second encapsulant laterally encapsulating the stacked-die structure and a redistribution layer disposed on the second encapsulant and the staked-die structure is provided. The stacked-die structure includes a first semiconductor die including a first active surface, a circuit layer disposed on the first active surface, a second semiconductor die including a second active surface facing towards the first active surface, a plurality of conductive features distributed at the circuit layer and electrically connected to the first and second semiconductor die and a first encapsulant encapsulating the second semiconductor die and the conductive features. A portion of the conductive features surrounds the second semiconductor die. The redistribution layer is electrically connected to the staked-die structure. A manufacturing method of a semiconductor package is also provided.