公开(公告)号：US20040195207A1

公开(公告)日：2004-10-07

申请号：US10690565

申请日：2003-10-23

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Hiroshi Tanaka

IPC: G01L021/30 ,  G01R031/00

CPC classification number: H01L21/67109

Abstract: In a substrate cleaning device, a substrate is held and is opposite to a plurality of heating/cooling components that can operate at different temperatures, the substrate and the heating/cooling components being separated to each other with a gap, which is filled with cleaning liquid. Chuck pins of resin with a low heat conductivity are used to hold the substrate, and the substrate is positioned such that it is not in contact with any component other than the chuck pins. In this way, the amount of etching can be adjusted for each portion of the substrate by controlling the temperature distribution on the substrate, thereby providing improved evenness of a surface within the plane of the substrate after a cleaning process.

Abstract translation: 在基板清洗装置中，基板被保持并且与可在不同温度下操作的多个加热/冷却部件相对，基板和加热/冷却部件被间隔开，间隙被填充清洁 液体。 使用导热率低的树脂的卡盘销来保持基板，并且将基板定位成使其不与卡盘销以外的任何部件接触。 以这种方式，可以通过控制基板上的温度分布来调整基板的每个部分的蚀刻量，从而在清洁处理之后提供改善的基板平面内的表面的均匀度。

公开(公告)号：US20040193291A1

公开(公告)日：2004-09-30

申请号：US10667672

申请日：2003-09-23

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Akiko Sakai

IPC: G05B013/02

CPC classification number: G06Q10/06 ,  Y02P90/14

Abstract: A production management method includes the steps of: pre-storing production information including delivery date information, manufacturing apparatus information and lot information; calculating a scheduled shipping date for each lot on the basis of the production information; reading a delivery date of the lot; calculating the number of delay days of the lot; outputting an alarm to the lot when the number of delay days is a positive number; and analyzing the main cause of the delay of the lot and generating an expedite instruction when the number of delay days is larger than 1.

Abstract translation: 一种生产管理方法，包括以下步骤：预先存储包括发货日期信息，制造装置信息和批量信息的生产信息; 根据生产信息计算每批的定期出货日期; 阅读批次的交货日期; 计算批次的延迟天数; 当延迟天数为正数时，向批次输出报警; 并分析当延误日数大于1时批次延误的主要原因，并产生快速指令。

公开(公告)号：US20040192008A1

公开(公告)日：2004-09-30

申请号：US10653214

申请日：2003-09-03

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Takeshi Matsunuma

IPC: H01L021/20

CPC classification number: H01L21/76801 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76834 ,  H01L21/76877 ,  H01L28/91

Abstract: A method of manufacturing a semiconductor device including an interconnection and a capacitor formed with a Cu layer in accordance with the present invention includes the steps of forming an interlayer insulation layer, forming an interconnection hole and a capacitor hole in the interlayer insulation layer, filling the interconnection hole with the Cu layer to form an interconnection layer, and partly filling the capacitor hole with the Cu layer to form one electrode of the capacitor. The step of filling the interconnection hole with the Cu layer to form the interconnection layer and the step of partly filling the capacitor hole with the Cu layer to form one electrode of the capacitor are performed in a single process step. Thus, manufacturing process of the semiconductor device can be simplified.

Abstract translation: 根据本发明的制造包括互连的半导体器件和由Cu层形成的电容器的方法包括以下步骤：在层间绝缘层中形成层间绝缘层，形成互连孔和电容器孔，填充 与Cu层的互连孔形成互连层，并用Cu层部分地填充电容器孔以形成电容器的一个电极。 用Cu层填充互连孔以形成互连层的步骤以及用Cu层部分地填充电容器孔以形成电容器的一个电极的步骤在单个工艺步骤中进行。 因此，可以简化半导体器件的制造工艺。

公开(公告)号：US20040191993A1

公开(公告)日：2004-09-30

申请号：US10819270

申请日：2004-04-07

Applicant: Renesas Technology Corp.

Inventor： Takashi Kobayashi

IPC: H01L021/336 ,  H01L029/788 ,  H01L021/8222

CPC classification number: H01L27/11526 ,  G11C16/0425 ,  G11C16/0491 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11546

Abstract: A nonvolatile semiconductor memory device having a memory cell comprising source/drain diffusion layer in p-well formed to a silicon substrate, a floating gate as a first gate, a control gate (word line) as a second gate, and a third gate, in which the floating gate and the p-well are isolated by a tunnel insulator film, the third gate and the p-well are isolated by a gate insulator film, the floating gate and the third gate are isolated by an insulator film, the floating gate and the word line (control gate) are isolated by a insulator film (ONO film), and the second gate film and the word line (control gate) are isolated by a silicon oxide film, respectively, wherein the thickness of the tunnel insulator film is made larger than the thickness of the gate insulator film. Accordingly, the reliability and access time of the device is improved.

公开(公告)号：US20040183122A1

公开(公告)日：2004-09-23

申请号：US10766188

申请日：2004-01-29

Applicant: Renesas Technology Corp.

Inventor： Toshiyuki Mine ,  Takashi Hashimoto ,  Senichi Nishibe ,  Nozomu Matsuzaki ,  Hitoshi Kume ,  Jiro Yugami

IPC: H01L029/788

CPC classification number: H01L29/66833 ,  G11C16/0466 ,  H01L21/28282 ,  H01L29/792

Abstract: A nonvolatile semiconductor memory device configured by a select MOS transistor provided with a gate insulator film and a select gate electrode, as well as a memory MOS transistor provided with a capacitor insulator film comprising a lower potential barrier film, a charge trapping film, and an upper potential barrier film, as well as a memory gate electrode. The charge trapping film is formed with a silicon oxynitride film and the upper potential barrier film is omitted or its thickness is limited to 1 nm and under to prevent the Gm degradation to be caused by the silicon oxynitride film, thereby lowering the erasure gate voltage. The charge trapping film is formed with a silicon oxynitride film used as a main charge trapping film and a silicon nitride film formed on or beneath the silicon oxynitride film so as to form a potential barrier effective only for holes. And, a hot-hole erasing method is employed to lower the erasure voltage.

Abstract translation: 一种非易失性半导体存储器件，由具有栅极绝缘膜和选择栅电极的选择MOS晶体管构成，以及具有电容绝缘膜的存储MOS晶体管，该MOS晶体管具有下部势垒膜，电荷俘获膜和 上电势势垒膜，以及存储栅电极。 电荷捕获膜由氧氮化硅膜形成，并且省略上电势阻挡膜或将其厚度限制在1nm以下，以防止由氮氧化硅膜引起的Gm劣化，从而降低擦除栅极电压。 电荷捕获膜由形成在氧氮化硅膜上或下面的主电荷俘获膜和氮化硅膜形成，以形成仅对孔有效的势垒。 并且，采用热孔擦除方法来降低擦除电压。

公开(公告)号：US20040182992A1

公开(公告)日：2004-09-23

申请号：US10817042

申请日：2004-04-05

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd. ,  Hitachi Tohbu Semiconductor, Ltd.

Inventor： Yasutoshi Aibara ,  Hiroki Nakajima ,  Eiki Imaizumi ,  Tatsuji Matsuura

IPC: H01J040/14 ,  H03M007/30 ,  H03M003/00

CPC classification number: H04N5/357 ,  H04N5/335 ,  H04N5/3577 ,  H04N5/3698 ,  H04N5/378

Abstract: An AD-converted digital video data is encoded by a difference encoding method before it is outputted and such encoded digital video data is then outputted, after it is converted to gray code or to a predetermined code in which a fixed value is added. Problems solved include noise that is generated when the AD conversion circuit outputs video data and that migrates into a CCD side via a power supply line on a printed circuit board, and noise that appears on a display image by migration into an input terminal side from an output circuit side via the power supply line and a semiconductor substrate within an AD conversion LSI.

Abstract translation: AD转换的数字视频数据在输出之前由差分编码方法编码，然后在将其转换为灰度代码或添加固定值的预定代码之后输出这样的编码数字视频数据。 解决的问题包括当AD转换电路输出视频数据并经由印刷电路板上的电源线迁移到CCD侧时产生的噪声，以及通过从显示图像迁移到输入端侧而出现在显示图像上的噪声 输出电路侧经由AD转换LSI内的电源线和半导体基板。

公开(公告)号：US20040181761A1

公开(公告)日：2004-09-16

申请号：US10694785

申请日：2003-10-29

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Makoto Kidera

IPC: G06F017/50

CPC classification number: G06F17/5036

Abstract: For simulation of an electric characteristic of a circuit including transistors, a plurality of transistors are arranged in a matrix pattern on the basis of sizes of the transistors, and data of the electric characteristic measured on first transistors among the plurality of transistors are stored in the matrix pattern. When a position of a second transistor different from the first transistors is specified in the matrix pattern, data of the electric characteristic of the second transistor are determined according to interpolation rules by using the measured data of the one or more first transistors if there are one or more first transistors in the plurality of first transistor at one or more positions adjacent to the position of the second transistor in the matrix pattern.

Abstract translation: 为了模拟包括晶体管的电路的电特性，基于晶体管的尺寸将多个晶体管布置成矩阵图案，并且将多个晶体管中的第一晶体管上测量的电特性的数据存储在 矩阵模式。 当在矩阵模式中指定与第一晶体管不同的第二晶体管的位置时，如果存在一个或多个第一晶体管的测量数据，则根据插值规则确定第二晶体管的电特性的数据 多个第一晶体管中的第一晶体管在与矩阵图案中的第二晶体管的位置相邻的一个或多个位置处。

公开(公告)号：US20040180628A1

公开(公告)日：2004-09-16

申请号：US10679461

申请日：2003-10-07

Applicant: Renesas Technology Corp.

Inventor： Shohei Moriwaki ,  Yoshifumi Azekawa ,  Osamu Chiba

IPC: H04B001/38

CPC classification number: H04L7/0008 ,  H04J3/0697

Abstract: A bus (3) includes a data bus (3a) and a clock bus (3b). The data bus (3a) is used for propagation of data MDIO conforming to the MDIO interface standards performed between a host controller IC (40) and a transceiver IC (1), and for propagation of data (SDA) conforming to the I2C standards performed between the transceiver IC (1) and a peripheral IC (2). Meanwhile, the clock bus (3b) is used for propagation of clock (MDC) conforming to the MDIO interface standards performed between the host controller IC (40) and the transceiver IC (1), and for propagation of clock (SCL) conforming to the I2C standards performed between the transceiver IC (1) and the peripheral IC (2).

Abstract translation: 总线（3）包括数据总线（3a）和时钟总线（3b）。 数据总线（3a）用于符合在主控制器IC（40）和收发器IC（1）之间执行的MDIO接口标准的数据MDIO的传播，并且用于传播符合I <2的数据（SDA） 在收发器IC（1）和外围IC（2）之间执行的C标准。 同时，时钟总线（3b）用于符合在主机控制器IC（40）和收发器IC（1）之间执行的MDIO接口标准的时钟传输（MDC），并用于符合 在收发器IC（1）和外围IC（2）之间执行的I 2 C标准。

公开(公告)号：US20040180522A1

公开(公告)日：2004-09-16

申请号：US10623563

申请日：2003-07-22

Applicant: Renesas Technology Corp.

Inventor： Yukio Nishida ,  Kazunobu Ohta

IPC: H01L021/4763

CPC classification number: H01L21/82385 ,  H01L21/28114 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42376

Abstract: A gate insulating film 4, two polysilicon films 5 and 7, and a silicon nitride film 9 are successively laminated on a semiconductor substrate 1 in this order. Each of the polysilicon films 5 and 7 contains phosphorus. The polysilicon film 5 has a region having a phosphorus concentration higher than that of the polysilicon film 7. Gate electrodes 10n, 10p, 40n, and 40p are formed on the gate insulating film 4 by partly etching the polysilicon films 5 and 7 and the silicon nitride film 9. In this case, the etching rate of the region of the polysilicon film 5, having a phosphorus concentration higher than that of the polysilicon film 7, is higher than that of the polysilicon film 7. Due to this difference, notches are formed at the bottom portions on side surfaces of respective gate electrodes 10p, 40n, and 40p.

Abstract translation: 依次将栅极绝缘膜4，两个多晶硅膜5和7以及氮化硅膜9依次层叠在半导体基板1上。 多晶硅膜5和7中的每一个都含有磷。 多晶硅膜5具有比多晶硅膜7的磷浓度高的区域。通过部分蚀刻多晶硅膜5和7，在栅极绝缘膜4上形成栅电极10n，10p，40n和40p，并且硅 在这种情况下，具有比多晶硅膜7高的磷浓度的多晶硅膜5的区域的蚀刻速率高于多晶硅膜7的蚀刻速率。由于这种差异，凹口是 形成在各个栅电极10p，40n和40p的侧表面的底部。

公开(公告)号：US20040180497A1

公开(公告)日：2004-09-16

申请号：US10793840

申请日：2004-03-08

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Yoshinori Tanaka ,  Masahiro Shimizu ,  Hideaki Arima

IPC: H01L031/119

CPC classification number: H01L27/0629 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10844 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91

Abstract: Obtained are a semiconductor device which can be implemented with high density of integration while ensuring a constant capacitor capacitance in high reliability and a method of fabricating the same. The semiconductor device, including a memory cell region and a peripheral circuit region, comprises an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode is formed in the memory cell region to upwardly extend beyond the upper surface of the insulating film on the major surface of the semiconductor substrate. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface. The upper surface of the insulating film is located between the top surface and the bottom surface of the capacitor lower electrode part.

Abstract translation: 获得的是可以以高可靠性确保恒定的电容器电容并实现高集成度的半导体器件及其制造方法。 包括存储单元区域和外围电路区域的半导体器件包括形成在半导体衬底的主表面上以从存储单元区域延伸到外围电路区域的上表面的绝缘膜。 在存储单元区域中形成电容器下电极，以向上延伸超过半导体衬底的主表面上的绝缘膜的上表面。 电容器上电极通过电介质膜形成在电容器下电极上，延伸到绝缘膜的上表面。 电容器下电极包括具有顶表面和底表面的电容器下电极部分。 绝缘膜的上表面位于电容器下电极部的顶表面和底表面之间。