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    ACCELERATED ERASURE CODING SYSTEM AND METHOD
    21.
    发明申请
    ACCELERATED ERASURE CODING SYSTEM AND METHOD 有权

    公开(公告)号：US20250096818A1

    公开(公告)日：2025-03-20

    申请号：US18968656

    申请日：2024-12-04

    Applicant: STREAMSCALE, INC.

    Inventor： Michael H. Anderson

    IPC: H03M13/15 ,  G06F11/10 ,  G06F12/02 ,  G06F12/06 ,  G11C29/52 ,  H03M13/00 ,  H03M13/11 ,  H03M13/13 ,  H03M13/37 ,  H04L1/00

    Abstract: An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

    ACCELERATED POLYNOMIAL CODING SYSTEM AND METHOD
    22.
    发明公开
    ACCELERATED POLYNOMIAL CODING SYSTEM AND METHOD 审中-公开

    公开(公告)号：US20240063825A1

    公开(公告)日：2024-02-22

    申请号：US18386183

    申请日：2023-11-01

    Applicant: STREAMSCALE, INC.

    Inventor： Michael H. Anderson

    IPC: H03M13/15 ,  G06F9/48 ,  G06F9/50 ,  G06F15/80 ,  H03M13/00

    CPC classification number: H03M13/1575 ,  G06F9/4881 ,  G06F9/5027 ,  G06F15/8007 ,  H03M13/154 ,  H03M13/6516

    Abstract: A system using accelerated error-correcting code in the storage and retrieval of data, wherein a single-instruction-multiple-data (SIMD) processor, SIMD instructions, non-volatile storage media, and an I/O controller implement a polynomial coding system including: a data matrix including at least one vector and including rows of at least one block of original data; a check matrix including more than two rows of at least one block of check data in the main memory; and a thread that executes on a SIMD CPU core and including: a parallel multiplier that multiplies the at least one vector of the data matrix by a single factor; and a parallel linear feedback shift register (LFSR) sequencer or a parallel syndrome sequencer configured to order load operations of the original data into at least one vector register of the SIMD CPU core and respectively compute the check data or syndrome data with the parallel multiplier.

    ACCELERATED ERASURE CODING SYSTEM AND METHOD
    23.
    发明申请
    ACCELERATED ERASURE CODING SYSTEM AND METHOD 有权

    公开(公告)号：US20220271777A1

    公开(公告)日：2022-08-25

    申请号：US17744329

    申请日：2022-05-13

    Applicant: STREAMSCALE, INC.

    Inventor： Michael H. Anderson

    IPC: H03M13/15 ,  G06F11/10 ,  H03M13/11 ,  H03M13/13 ,  G06F12/02 ,  G06F12/06 ,  H03M13/37 ,  H04L1/00 ,  H03M13/00 ,  G11C29/52

    Abstract: An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

    Accelerated erasure coding system and method
    24.
    发明授权
    Accelerated erasure coding system and method 有权

    公开(公告)号：US10666296B2

    公开(公告)日：2020-05-26

    申请号：US16358602

    申请日：2019-03-19

    Applicant: STREAMSCALE, INC.

    Inventor： Michael H. Anderson

    IPC: H03M13/15 ,  G06F11/10 ,  H03M13/11 ,  H03M13/13 ,  G06F12/02 ,  G06F12/06 ,  H03M13/37 ,  H04L1/00 ,  H03M13/00 ,  G11C29/52

    Abstract: An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

    Using parity data for concurrent data authentication, correction, compression, and encryption
    25.
    发明授权
    Using parity data for concurrent data authentication, correction, compression, and encryption 有权

    公开(公告)号：US10664347B2

    公开(公告)日：2020-05-26

    申请号：US16277869

    申请日：2019-02-15

    Applicant: STREAMSCALE, INC.

    Inventor： Michael H. Anderson

    IPC: G06F11/10 ,  H03M13/00 ,  H03M13/37 ,  H03M13/15 ,  H03M13/13 ,  G06F12/06 ,  G06F12/02 ,  H04L1/00 ,  H03M13/11 ,  G06F3/06

    Abstract: A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

    ACCELERATED POLYNOMIAL CODING SYSTEM AND METHOD
    29.
    发明公开
    ACCELERATED POLYNOMIAL CODING SYSTEM AND METHOD 审中-公开

    公开(公告)号：US20230378979A1

    公开(公告)日：2023-11-23

    申请号：US17747828

    申请日：2022-05-18

    Applicant: STREAMSCALE, INC.

    Inventor： Michael H. Anderson

    IPC: H03M13/15 ,  H03M13/00 ,  G06F9/48 ,  G06F9/50 ,  G06F15/80

    CPC classification number: H03M13/1575 ,  H03M13/154 ,  H03M13/6516 ,  G06F9/4881 ,  G06F9/5027 ,  G06F15/8007

    Abstract: A system using accelerated error-correcting code in the storage and retrieval of data, wherein a single-instruction-multiple-data (SIMD) processor, SIMD instructions, non-volatile storage media, and an I/O controller implement a polynomial coding system including: a data matrix including at least one vector and including rows of at least one block of original data; a check matrix including more than two rows of at least one block of check data in the main memory; and a thread that executes on a SIMD CPU core and including: a parallel multiplier that multiplies the at least one vector of the data matrix by a single factor; and a parallel linear feedback shift register (LFSR) sequencer or a parallel syndrome sequencer configured to order load operations of the original data into at least one vector register of the SIMD CPU core and respectively compute the check data or syndrome data with the parallel multiplier.

    Using parity data for concurrent data authentication, correction, compression, and encryption
    30.
    发明授权
    Using parity data for concurrent data authentication, correction, compression, and encryption 有权

    公开(公告)号：US11500723B2

    公开(公告)日：2022-11-15

    申请号：US16855901

    申请日：2020-04-22

    Applicant: STREAMSCALE, INC.

    Inventor： Michael H. Anderson

    IPC: G06F11/10 ,  H03M13/00 ,  H03M13/37 ,  H03M13/15 ,  H03M13/13 ,  G06F12/06 ,  G06F12/02 ,  H04L1/00 ,  H03M13/11 ,  G06F3/06

    Abstract: A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

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