中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

40 records (took 0.023 seconds)

    FORMING STRUCTURES WITH BOTTOM-UP FILL TECHNIQUES
    21.
    发明申请
    FORMING STRUCTURES WITH BOTTOM-UP FILL TECHNIQUES 有权

    公开(公告)号：US20230005744A1

    公开(公告)日：2023-01-05

    申请号：US17850370

    申请日：2022-06-27

    Applicant: ASM IP Holding B.V.

    Inventor： Caleb Miskin ,  Omar Elleuch ,  Peter Westrom ,  Rami Khazaka ,  Qi Xie ,  Alexandros Demos

    IPC: H01L21/02 ,  C23C16/455

    Abstract: A method of forming a structure includes supporting a substrate within a reaction chamber of a semiconductor processing system, the substrate having a recess with a bottom surface and a sidewall surface extending upwards from the bottom surface of the recess. A film is deposited within the recess and onto the bottom surface and the sidewall surface of the recess, the film having a bottom segment overlaying the bottom surface of the recess and a sidewall segment deposited onto the sidewall surface of the recess. The sidewall segment of the film is removed while at least a portion bottom segment of the film is retained within the recess, the sidewall segment of the film removed from the sidewall surface more rapidly than removing the bottom segment of the film from the bottom surface of the recess. Semiconductor processing systems and structures formed using the method are also described.

    HIGH PERFORMANCE SUSCEPTOR APPARATUS
    23.
    发明申请
    HIGH PERFORMANCE SUSCEPTOR APPARATUS 有权

    公开(公告)号：US20220181193A1

    公开(公告)日：2022-06-09

    申请号：US17457605

    申请日：2021-12-03

    Applicant: ASM IP HOLDING B.V.

    Inventor： Peipei Gao ,  Wentao Wang ,  Xing Lin ,  Han Ye ,  Ion Hong Chao ,  Siyao Luan ,  Alexandros Demos ,  Fan Gao

    IPC: H01L21/687

    Abstract: A substrate support and lift assembly configured to support and lift a substrate from a susceptor is disclosed. The substrate support and lift assembly can include a susceptor support and a lift pin. The susceptor support can be configured to support the susceptor thereon. The susceptor support includes a plurality of support arms each extending radially from a central portion of the susceptor support to a terminus. Each of the plurality of support arms includes an aperture extending therethrough. The lift pin can be configured to fit through the aperture of a corresponding support arm to lift a substrate on the susceptor.

    SUSCEPTOR FOR SEMICONDUCTOR SUBSTRATE PROCESSING
    24.
    发明申请
    SUSCEPTOR FOR SEMICONDUCTOR SUBSTRATE PROCESSING 有权

    公开(公告)号：US20210125853A1

    公开(公告)日：2021-04-29

    申请号：US17075504

    申请日：2020-10-20

    Applicant: ASM IP HOLDING B.V.

    Inventor： Saket Rathi ,  Shiva K.T. Rajavelu Muralidhar ,  Siyao Luan ,  Alexandros Demos ,  Xing Lin

    IPC: H01L21/687 ,  H01L21/324 ,  H01L21/67 ,  H01L21/268

    Abstract: A susceptor for semiconductor substrate processing is disclosed herein. In some embodiments, the susceptor may comprise an inner susceptor portion and an outer susceptor portion. The susceptor portions may self-align via complementary features, such as tabs on the outer susceptor and recesses on the inner susceptor portion. The inner susceptor portion may contain several contact pads with which to support a wafer during semiconductor processing. In some embodiments, the contact pads are hemispherical to reduce contact area with the wafer, thereby reducing risk of backside damage. The inner susceptor portion may contain a cavity with which to receive a thermocouple. In some embodiments, the diameter of the cavity is greater than the diameter of the thermocouple such that the thermocouple does not contact the walls of the cavity during processing, thereby providing highly accurate temperature measurements.

    CHAMBER ARRANGEMENTS, SEMICONDUCTOR PROCESSING SYSTEMS INCLUDING CHAMBER ARRANGEMENTS AND RELATED MATERIAL LAYER DEPOSITION METHODS
    26.
    发明申请
    CHAMBER ARRANGEMENTS, SEMICONDUCTOR PROCESSING SYSTEMS INCLUDING CHAMBER ARRANGEMENTS AND RELATED MATERIAL LAYER DEPOSITION METHODS 有权

    公开(公告)号：US20250112064A1

    公开(公告)日：2025-04-03

    申请号：US18900352

    申请日：2024-09-27

    Applicant: ASM IP Holding B.V.

    Inventor： Amir Kajbafvala ,  Arun Murali ,  Caleb Miskin ,  Frederick Aryeetey ,  Alexandros Demos

    IPC: H01L21/67

    Abstract: A chamber arrangement for a semiconductor processing system includes a chamber body, a substrate support, a first chamber pyrometer, and a second chamber pyrometer. The chamber body has an exterior surface, a hollow interior, and the substrate support is supported for rotation within the interior of the chamber body. The first chamber pyrometer and second chamber pyrometer are optically coupled to the exterior surface of the chamber body. The first chamber pyrometer is configured to acquire a first temperature measurement at a first location on the exterior surface of the chamber body, and the second chamber pyrometer is configured to acquire a second temperature measurement at a second location on the exterior surface of the chamber body. The second location is offset from the first location to throttle temperature across the exterior surface of the chamber body between the first location and the second location. Material layer deposition methods and computer program products are also described.

    METHODS OF FORMING SEMICONDUCTOR STRUCTURES, SEMICONDUCTOR PROCESSING SYSTEMS AND RELATED COMPUTER PROGRAM PRODUCTS
    27.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR STRUCTURES, SEMICONDUCTOR PROCESSING SYSTEMS AND RELATED COMPUTER PROGRAM PRODUCTS 有权

    公开(公告)号：US20250079167A1

    公开(公告)日：2025-03-06

    申请号：US18815636

    申请日：2024-08-26

    Applicant: ASM IP Holding B.V.

    Inventor： Ernesto Suarez ,  Amir Kajbafvala ,  Arun Murali ,  Caleb Miskin ,  Alexandros Demos

    IPC: H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/167

    Abstract: A method of forming a semiconductor structure includes seating a substrate on a substrate support arranged within a chamber arrangement of a semiconductor processing system, flowing a boron-containing precursor to the chamber arrangement at a first boron-containing precursor mass flow rate, and depositing a first portion of a first SiGe:B layer using the boron-containing precursor. Mass flow rate of the boron-containing precursor to an intermediate boron-containing precursor flow rate, a second portion of the first SiGe:B layer is deposited using the boron-containing precursor, mass flow rate of the boron-containing precursor to the chamber arrangement is further increased to a second boron-containing precursor mass flow rate, and a second SiGe:B layer is deposited onto the first SiGe:B layer using the boron-containing precursor, the increase in the mass flow rate of the boron-containing precursor to the intermediate boron-containing precursor mass flow rate limits boron concentration at a first SiGe:B layer-to-second SiGe:B layer interface defined between the first SiGe:B layer and the second SiGe:B layer to less than a boron concentration within the second SiGe:B layer. Semiconductor processing systems and related computer program products are also provided.

Patent Agency Ranking