公开(公告)号：US20210027437A1

公开(公告)日：2021-01-28

申请号：US17069523

申请日：2020-10-13

Applicant: ATI Technologies ULC

Inventor： Jie Zhou ,  David I. J. Glen

IPC: G06T5/00 ,  H04N5/235

Abstract: There are many instances where a standard dynamic range (“SDR”) overlay is displayed over high dynamic range (“HDR”) content on HDR displays. Because the overlay is SDR, the maximum brightness of the overlay is much lower than the maximum brightness of the HDR content, which can lead to the SDR elements being obscured if those elements have at least some transparency. The present disclosure provides techniques including modifying the luminance of either or both of the HDR and SDR content when an SDR layer with some transparency is displayed over HDR content. A variety of techniques are provided. In one example, a fixed adjustment is applied to pixels of one or both of the SDR layer and the HDR layer. The fixed adjustment comprises decreasing the luminance of the HDR layer and/or increasing the luminance of the SDR layer. In another example, a variable adjustment is applied.

公开(公告)号：US10210845B2

公开(公告)日：2019-02-19

申请号：US15966525

申请日：2018-04-30

Applicant: ATI Technologies ULC

Inventor： David I. J. Glen ,  Syed A. Hussain

IPC: G09G5/395 ,  G09G5/00

Abstract: Briefly, methods and apparatus provide image content to, and display image content on, displays with a variable refresh rate that reduce frame delays and avoid display image flickering problems. In one example, the methods and apparatus are operative to vary a display's refresh rate by varying a current frame's vertical blanking period by re-providing the current frame for display prior to providing a new frame for display. In this fashion, the displaying of a new frame may be advanced by assuring that a new frame can be provided for display as soon as it has been rendered and available for display. In addition, by re-providing the current frame for display prior to providing a new frame for display, new frames may be provided for display at rates within a safe rate range such that display image flickering issues are avoided or reduced.

公开(公告)号：US12190847B2

公开(公告)日：2025-01-07

申请号：US17407981

申请日：2021-08-20

Applicant: ATI Technologies ULC

Inventor： Keith Lee ,  David I. J. Glen ,  Jie Zhou ,  Yuxin Chen

IPC: G09G5/02 ,  G09G5/06

Abstract: Systems, apparatuses, and methods for reducing three dimensional (3D) lookup table (LUT) interpolation error while minimizing on-chip storage are disclosed. A processor generates a plurality of mappings from a first gamut to a second gamut at locations interspersed throughout a 3D representation of the pixel component space. For example, in one implementation, the processor calculates mappings for 17×17×17 vertices within the 3D representation. Other implementations can include other numbers of vertices. Rather than increasing the number of vertices to reduce interpolation error, the processor calculates mappings for centroids of the sub-cubes defined by the vertices within the 3D representation of the first gamut. This results in a smaller increase to the LUT size as compared to increasing the number of vertices. The centroid mappings are used for performing tetrahedral interpolation to map source pixels in the first gamut into the second gamut with a reduced amount of interpolation error.

公开(公告)号：US12148134B2

公开(公告)日：2024-11-19

申请号：US18309568

申请日：2023-04-28

Applicant: ATI Technologies ULC

Inventor： Jie Zhou ,  David I. J. Glen

IPC: G06K9/40 ,  G06T5/92 ,  H04N23/741

Abstract: There are many instances where a standard dynamic range (“SDR”) overlay is displayed over high dynamic range (“HDR”) content on HDR displays. Because the overlay is SDR, the maximum brightness of the overlay is much lower than the maximum brightness of the HDR content, which can lead to the SDR elements being obscured if those elements have at least some transparency. The present disclosure provides techniques including modifying the luminance of either or both of the HDR and SDR content when an SDR layer with some transparency is displayed over HDR content. A variety of techniques are provided. In one example, a fixed adjustment is applied to pixels of one or both of the SDR layer and the HDR layer. The fixed adjustment comprises decreasing the luminance of the HDR layer and/or increasing the luminance of the SDR layer. In another example, a variable adjustment is applied.

公开(公告)号：US12014700B2

公开(公告)日：2024-06-18

申请号：US18089837

申请日：2022-12-28

Applicant: ATI TECHNOLOGIES ULC

Inventor： Syed Athar Hussain ,  Anthony W L Koo ,  David I. J. Glen

IPC: G09G5/12 ,  G06T1/20 ,  G06T9/00 ,  G09G5/00

CPC classification number: G09G5/00 ,  G06T1/20 ,  G06T9/00 ,  G09G2330/023 ,  G09G2360/18 ,  G09G2370/12

Abstract: A graphics processing unit (GPU) of a processing system transmits pixel data for a frame to a display in a compressed burst, so that the pixel data is communicated at a rate that is higher than the rate at which the display scans out the pixel data to refresh the frame at a display panel. By transmitting pixel data for the frame in a compressed burst, the GPU shortens the time spent transmitting the pixel data and extends the time before the next frame of pixel data is to be transmitted. During the extended time before the next frame of pixel data is to be transmitted, the GPU saves power by placing portions of the processing system in a reduced power mode.

公开(公告)号：US11763778B2

公开(公告)日：2023-09-19

申请号：US17884793

申请日：2022-08-10

Applicant: ATI TECHNOLOGIES ULC

Inventor： David I. J. Glen

IPC: G09G5/36 ,  G09G3/20

CPC classification number: G09G5/363 ,  G09G3/20 ,  G09G2310/061 ,  G09G2310/08

Abstract: A graphics processing unit (GPU) includes a timing reference one or more processors configured to generate and provide, based on the timing reference, frames to a display system that supports variable refresh rates. The frames include a vertical blanking region having a first duration. The display system transmits information indicating an operation to be performed by the display system during the vertical blanking region of one or more subsequent frames. The one or more processors are configured to increase the first duration to a second duration in response to receiving the information indicating an operation to be performed by the display system during the vertical blanking region of at least one subsequent frame. In some cases, the first duration of the vertical blanking region is a minimum duration that corresponds to a maximum refresh rate supported by the display system.

公开(公告)号：US11417295B2

公开(公告)日：2022-08-16

申请号：US17030676

申请日：2020-09-24

Applicant: ATI TECHNOLOGIES ULC

Inventor： David I. J. Glen

IPC: G09G3/20 ,  G09G5/36

Abstract: A graphics processing unit (GPU) includes a timing reference one or more processors configured to generate and provide, based on the timing reference, frames to a display system that supports variable refresh rates. The frames include a vertical blanking region having a first duration. The display system transmits information indicating an operation to be performed by the display system during the vertical blanking region of one or more subsequent frames. The one or more processors are configured to increase the first duration to a second duration in response to receiving the information indicating an operation to be performed by the display system during the vertical blanking region of at least one subsequent frame. In some cases, the first duration of the vertical blanking region is a minimum duration that corresponds to a maximum refresh rate supported by the display system.

公开(公告)号：US11100889B2

公开(公告)日：2021-08-24

申请号：US16289260

申请日：2019-02-28

Applicant: ATI Technologies ULC

Inventor： Keith Lee ,  David I. J. Glen ,  Jie Zhou ,  Yuxin Chen

IPC: G09G5/02 ,  G09G5/06

Abstract: Systems, apparatuses, and methods for reducing three dimensional (3D) lookup table (LUT) interpolation error while minimizing on-chip storage are disclosed. A processor generates a plurality of mappings from a first gamut to a second gamut at locations interspersed throughout a 3D representation of the pixel component space. For example, in one implementation, the processor calculates mappings for 17×17×17 vertices within the 3D representation. Other implementations can include other numbers of vertices. Rather than increasing the number of vertices to reduce interpolation error, the processor calculates mappings for centroids of the sub-cubes defined by the vertices within the 3D representation of the first gamut. This results in a smaller increase to the LUT size as compared to increasing the number of vertices. The centroid mappings are used for performing tetrahedral interpolation to map source pixels in the first gamut into the second gamut with a reduced amount of interpolation error.

公开(公告)号：US09473678B2

公开(公告)日：2016-10-18

申请号：US14518919

申请日：2014-10-20

Applicant: ATI Technologies ULC

Inventor： David I. J. Glen

IPC: H04N5/21 ,  G09G5/00 ,  H04N5/14 ,  H04N21/41 ,  H04N21/436

CPC classification number: H04N5/21 ,  G09G5/006 ,  G09G2350/00 ,  G09G2370/047 ,  G09G2370/10 ,  G09G2370/12 ,  H04N5/14 ,  H04N21/4113 ,  H04N21/436

Abstract: To apportion desired video processing between a video source device and a video sink device, at one of the devices, and based upon an indication of video processing algorithms of which the other device is capable and an indication of video processing algorithms of which the one device is capable, a set of video processing algorithms for achieving desired video processing is identified. The identified set of video processing algorithms is classified into a first subset of algorithms for performance by the other device and a second subset of algorithms for performance by the one device. At least one command for causing the other device to effect the first subset of video processing algorithms is sent. The one device may be configured to effect the second subset of algorithms.

Abstract translation: 为了在视频源设备和视频接收设备之间的一个设备上分配所需的视频处理，并且基于其他设备能够执行的视频处理算法的指示以及一个设备的视频处理算法的指示 能够识别用于实现期望的视频处理的一组视频处理算法。 所识别的一组视频处理算法被分类为用于由另一设备执行性能的算法的第一子集，以及由该设备执行性能的第二子算法子集。 发送用于使另一设备影响视频处理算法的第一子集的至少一个命令。 一个设备可以被配置为实现算法的第二子集。

公开(公告)号：US09124855B2

公开(公告)日：2015-09-01

申请号：US13687415

申请日：2012-11-28

Applicant: ATI Technologies ULC

Inventor： David I. J. Glen

IPC: H04N9/79 ,  H04N5/76 ,  H04N5/765

CPC classification number: H04N9/79 ,  H04N5/76 ,  H04N5/765

Abstract: A method and apparatus for video stream processing is implemented in a monitor scaler chip (MSC). The MSC receives the video stream and determines whether the video stream includes copy protected content. The MSC routes the video stream based upon the determination.

Abstract translation: 用于视频流处理的方法和装置在监视器缩放器芯片（MSC）中实现。 MSC接收视频流并确定视频流是否包括复制保护内容。 MSC根据确定路由视频流。