公开(公告)号：US11688031B2

公开(公告)日：2023-06-27

申请号：US17060942

申请日：2020-10-01

Applicant: ATI TECHNOLOGIES ULC

Inventor： Anthony W L Koo ,  Syed Athar Hussain ,  David I. J. Glen

IPC: G09G5/393 ,  G06T1/20 ,  G09G3/36

CPC classification number: G06T1/20 ,  G09G3/3618 ,  G09G2340/16 ,  G09G2360/18

Abstract: A display system receives first timing information prior to the display system entering a panel self-refresh (PSR) mode. The display system supports a range of refresh rates. Prior to the display system entering the PSR mode, first timing information indicating a first refresh rate that is lower than a maximum refresh rate supported by the display system is received by the display system. The display system then refreshes images at a second refresh rate that is less than or equal to the first refresh rate using a frame stored in a buffer prior to entering the PSR mode. In some cases, the processing unit also receives second timing information from the display system in response to initiating an exit from a panel self-refresh (PSR) mode. The second timing information indicates a current scanout line that is used to schedule transmission of a subsequent frame.

公开(公告)号：US20200279538A1

公开(公告)日：2020-09-03

申请号：US16289260

申请日：2019-02-28

Applicant: ATI Technologies ULC

Inventor： Keith Lee ,  David I. J. Glen ,  Jie Zhou ,  Yuxin Chen

IPC: G09G5/06

Abstract: Systems, apparatuses, and methods for reducing three dimensional (3D) lookup table (LUT) interpolation error while minimizing on-chip storage are disclosed. A processor generates a plurality of mappings from a first gamut to a second gamut at locations interspersed throughout a 3D representation of the pixel component space. For example, in one implementation, the processor calculates mappings for 17×17×17 vertices within the 3D representation. Other implementations can include other numbers of vertices. Rather than increasing the number of vertices to reduce interpolation error, the processor calculates mappings for centroids of the sub-cubes defined by the vertices within the 3D representation of the first gamut. This results in a smaller increase to the LUT size as compared to increasing the number of vertices. The centroid mappings are used for performing tetrahedral interpolation to map source pixels in the first gamut into the second gamut with a reduced amount of interpolation error.

公开(公告)号：US09984664B2

公开(公告)日：2018-05-29

申请号：US14661868

申请日：2015-03-18

Applicant: ATI Technologies ULC

Inventor： David I. J. Glen ,  Syed A. Hussain

IPC: G09G5/18 ,  G09G5/00 ,  G09G5/395

CPC classification number: G09G5/395 ,  G09G5/005 ,  G09G2320/0247 ,  G09G2340/02 ,  G09G2340/0435 ,  G09G2360/08

Abstract: Briefly, methods and apparatus provide image content to, and display image content on, displays with a variable refresh rate that reduce frame delays and avoid display image flickering problems. In one example, the methods and apparatus are operative to vary a display's refresh rate by varying a current frame's vertical blanking period by re-providing the current frame for display prior to providing a new frame for display. In this fashion, the displaying of a new frame may be advanced by assuring that a new frame can be provided for display as soon as it has been rendered and available for display. In addition, by re-providing the current frame for display prior to providing a new frame for display, new frames may be provided for display at rates within a safe rate range such that display image flickering issues are avoided or reduced.

公开(公告)号：US20160275916A1

公开(公告)日：2016-09-22

申请号：US14661868

申请日：2015-03-18

Applicant: ATI Technologies ULC

Inventor： David I. J. Glen ,  Syed A. Hussain

IPC: G09G5/18 ,  G06T1/60 ,  G09G5/00

CPC classification number: G09G5/395 ,  G09G5/005 ,  G09G2320/0247 ,  G09G2340/02 ,  G09G2340/0435 ,  G09G2360/08

Abstract: Briefly, methods and apparatus provide image content to, and display image content on, displays with a variable refresh rate that reduce frame delays and avoid display image flickering problems. In one example, the methods and apparatus are operative to vary a display's refresh rate by varying a current frame's vertical blanking period by re-providing the current frame for display prior to providing a new frame for display. In this fashion, the displaying of a new frame may be advanced by assuring that a new frame can be provided for display as soon as it has been rendered and available for display. In addition, by re-providing the current frame for display prior to providing a new frame for display, new frames may be provided for display at rates within a safe rate range such that display image flickering issues are avoided or reduced.

Abstract translation: 简而言之，方法和装置以可减少帧延迟并避免显示图像闪烁问题的可变刷新速率为显示器提供图像内容和显示图像内容。 在一个示例中，方法和装置可操作以通过在提供用于显示的新帧之前重新提供用于显示的当前帧来改变当前帧的垂直消隐周期来改变显示器的刷新率。 以这种方式，可以通过确保新的帧可以被提供用于显示，一旦它被渲染并且可用于显示，就可以提高新帧的显示。 此外，通过在提供用于显示的新帧之前重新提供用于显示的当前帧，可以提供新帧以用于以安全速率范围内的速率显示，使得避免或减少显示图像闪烁问题。

公开(公告)号：US11948534B2

公开(公告)日：2024-04-02

申请号：US17877540

申请日：2022-07-29

Applicant: ATI TECHNOLOGIES ULC

Inventor： Jun Lei ,  Syed Athar Hussain ,  David I. J. Glen ,  Rajeevan Panchacharamoorthy ,  Fatemeh Amirnavaei ,  David Galiffi ,  Arshad Rahman ,  Boris Ivanovic

IPC: G09G5/12 ,  G06F3/14

CPC classification number: G09G5/12 ,  G06F3/1431 ,  G06F3/1446 ,  G09G2360/04

Abstract: A display system modifies display cycles of one or more displays to perform a system operation while avoiding visual perturbations at the one or more displays. The display system modifies, synchronizes, or both, blanking periods of the one or more displays such that blanking periods equal or exceed a blackout duration and overlap for at least the blackout duration. Then the system performs the system operation during an overlapping portion of the one or more blanking periods, where the system operation reduces availability of display data at the one or more displays.

公开(公告)号：US11657483B2

公开(公告)日：2023-05-23

申请号：US17069523

申请日：2020-10-13

Applicant: ATI Technologies ULC

Inventor： Jie Zhou ,  David I. J. Glen

IPC: G06T5/00 ,  H04N5/235

CPC classification number: G06T5/009 ,  H04N5/2355 ,  G06T2207/20208

Abstract: There are many instances where a standard dynamic range (“SDR”) overlay is displayed over high dynamic range (“HDR”) content on HDR displays. Because the overlay is SDR, the maximum brightness of the overlay is much lower than the maximum brightness of the HDR content, which can lead to the SDR elements being obscured if those elements have at least some transparency. The present disclosure provides techniques including modifying the luminance of either or both of the HDR and SDR content when an SDR layer with some transparency is displayed over HDR content. A variety of techniques are provided. In one example, a fixed adjustment is applied to pixels of one or both of the SDR layer and the HDR layer. The fixed adjustment comprises decreasing the luminance of the HDR layer and/or increasing the luminance of the SDR layer. In another example, a variable adjustment is applied.

公开(公告)号：US11551632B2

公开(公告)日：2023-01-10

申请号：US17029736

申请日：2020-09-23

Applicant: ATI TECHNOLOGIES ULC

Inventor： Syed Athar Hussain ,  Anthony W L Koo ,  David I. J. Glen

IPC: G06F13/00 ,  G09G5/00 ,  G06T1/20 ,  G06T9/00

Abstract: A graphics processing unit (GPU) of a processing system transmits pixel data for a frame to a display in a compressed burst, so that the pixel data is communicated at a rate that is higher than the rate at which the display scans out the pixel data to refresh the frame at a display panel. By transmitting pixel data for the frame in a compressed burst, the GPU shortens the time spent transmitting the pixel data and extends the time before the next frame of pixel data is to be transmitted. During the extended time before the next frame of pixel data is to be transmitted, the GPU saves power by placing portions of the processing system in a reduced power mode.

公开(公告)号：US10368108B2

公开(公告)日：2019-07-30

申请号：US13723486

申请日：2012-12-21

Applicant: ATI Technologies ULC

Inventor： David I. J. Glen

IPC: H04N5/272 ,  H04N21/2343 ,  H04N21/43 ,  H04N21/434 ,  H04N21/47

Abstract: A video source, a display and a method of processing multilayered video are disclosed. The video source decodes a multilayered video bit stream to transmit synchronized streams of decompressed video images and corresponding overlay images to an interconnected display. The display receives separate streams of video and overlay images. Transmission and reception of corresponding video and overlay images is synchronized in time. A video image received in the display can be selectively processed separately from its corresponding overlay image. The video image as processed at the display is later composited with its corresponding overlay image to form an output image for display.

公开(公告)号：US09924134B2

公开(公告)日：2018-03-20

申请号：US14313522

申请日：2014-06-24

Applicant: ATI Technologies ULC

Inventor： David I. J. Glen

IPC: G06T1/00 ,  G09G5/18 ,  H04N7/01 ,  G09G3/20 ,  H04N5/46 ,  H04N21/4402 ,  H04N21/443 ,  H04N21/462 ,  H04N21/41

CPC classification number: H04N7/0127 ,  G09G3/20 ,  G09G2340/0435 ,  H04N5/46 ,  H04N21/4122 ,  H04N21/440281 ,  H04N21/4436 ,  H04N21/4621

Abstract: An image rendering unit (IRU) of a device determines the dynamic frame rate capabilities (DFRCs) of a display and an image frame rate of content to be displayed. Preferably, the DFRCs are stored in a storage device deployed within the display itself. Based on the DFRCs and the image frame rate for the content, the IRU determines an updated frame rate and thereafter provides the content to the display at the updated frame rate. Where control of power consumption is desired, selection of a reduced frame rate can effect a power savings. In this manner, the present invention provides flexible control over display frame rates and/or power consumption of the device.

公开(公告)号：US12039626B2

公开(公告)日：2024-07-16

申请号：US17555955

申请日：2021-12-20

Applicant: ATI Technologies ULC

Inventor： David I. J. Glen

IPC: G06T1/20 ,  G06F3/14 ,  G06F3/04847

CPC classification number: G06T1/20 ,  G06F3/14 ,  G06F3/04847

Abstract: An image generation apparatus includes at least a first configuration register that includes first configuration data for configuring parameters of an image processor, at least a second configuration register that includes second configuration data for configuring the parameters of a same image processing pipeline in the image processor, multiplexing logic coupled to the first configuration register and to the second configuration register, control logic that controls the multiplexing logic to in a non-demonstration mode select one of the first or second configuration registers to produce a first image frame and operative in a demonstration mode to provide both the first and second configuration data for the same image processing pipeline of the image processor to use for generating different regions of an image frame.