公开(公告)号：US20210265273A1

公开(公告)日：2021-08-26

申请号：US16798152

申请日：2020-02-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien Lin CHANG CHIEN ,  Chiu-Wen LEE ,  Ian HU ,  Chang Chi LEE

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/48

Abstract: A semiconductor device package includes a plurality of semiconductor chips and an interposer structure. The interposer structure has a plurality of tiers for accommodating the plurality of semiconductor chips. The interposer structure includes at least one conductive via connecting to a pad of the plurality of semiconductor chips.

公开(公告)号：US20180158766A1

公开(公告)日：2018-06-07

申请号：US15884197

申请日：2018-01-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien Lin CHANG CHIEN ,  Chin-Li KAO ,  Chang Chi LEE ,  Chih-Pin HUNG

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48

Abstract: A method of manufacturing a semiconductor package includes: (a) providing a carrier; (b) disposing a dielectric layer and a conductive pad on the carrier; (c) disposing a redistribution layer on the dielectric layer to electrically connect to the conductive pad; (d) connecting a die to the redistribution layer; (e) removing at least a portion of the carrier to expose the conductive pad; and (f) disposing an electrical contact to electrically connect to the conductive pad.

公开(公告)号：US20170207153A1

公开(公告)日：2017-07-20

申请号：US15479074

申请日：2017-04-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien Lin CHANG CHIEN ,  Chin-Li KAO ,  Chang Chi LEE ,  Chih-Pin HUNG

IPC: H01L23/498 ,  H01L25/00 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/562 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06586

Abstract: In one or more embodiments, a semiconductor package includes a redistribution layer, a conductive pad, a dielectric layer, a silicon layer, and a conductive contact. The redistribution layer includes a first surface and a second surface opposite to the first surface. The conductive pad is on the first surface of the redistribution layer. The dielectric layer is disposed on the first surface of the redistribution layer to cover a first portion of the conductive pad and to expose a second portion of the conductive pad. The silicon layer is disposed on the dielectric layer, the silicon layer having a recess to expose the second portion of the conductive pad. The conductive contact is disposed over the silicon layer and extends into the recess of the silicon layer.

公开(公告)号：US20250022848A1

公开(公告)日：2025-01-16

申请号：US18904050

申请日：2024-10-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chang Chi LEE ,  Jung Jui KANG ,  Chiu-Wen LEE ,  Li Chieh CHEN

IPC: H01L25/065 ,  H01L23/538

Abstract: A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first processing element, a first I/O element, a second processing element, and a second I/O element. The first processing element is on a substrate. The first I/O element is on the substrate and electrically connected to the first processing element. The second processing element is on the substrate. The second I/O element is on the substrate and electrically connected to the second processing element. The first I/O element is electrically connected to and physically separated from the second I/O element.

公开(公告)号：US20240128193A1

公开(公告)日：2024-04-18

申请号：US17966698

申请日：2022-10-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Pao-Nan LEE ,  Chang Chi LEE ,  Jung Jui KANG

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L23/552 ,  H01L25/16

CPC classification number: H01L23/5386 ,  H01L23/3677 ,  H01L23/49866 ,  H01L23/5385 ,  H01L23/552 ,  H01L24/16 ,  H01L25/162 ,  H01L25/165 ,  H01L2224/16225 ,  H01L2924/14252 ,  H01L2924/1427 ,  H01L2924/1434 ,  H01L2924/19041 ,  H01L2924/3025

Abstract: An electronic module is disclosed. The electronic module includes an electronic component and an interconnection structure disposed over the electronic component. The interconnection structure comprises a first region and a second region different from the first region. The first region is configured to transmit a power from outside of the electronic module to the electronic component. The second region is configured to dissipate heat from the electronic component.

公开(公告)号：US20240038679A1

公开(公告)日：2024-02-01

申请号：US17877799

申请日：2022-07-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Pao-Nan LEE ,  Jung Jui KANG ,  Chang Chi LEE

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L23/3128 ,  H01L24/16 ,  H01L2924/3025 ,  H01L2924/15311

Abstract: The present disclosure provides an electronic device. The electronic device includes a first electronic component, a first conductive element, and a voltage regulator. The voltage regulator is disposed adjacent to the first electronic component. The voltage regulator is configured to regulate a first voltage from the first EMI shielding layer and to provide the first electronic component with a second voltage.

公开(公告)号：US20230163077A1

公开(公告)日：2023-05-25

申请号：US17535400

申请日：2021-11-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chang Chi LEE ,  Chiu-Wen LEE ,  Jung Jui KANG

IPC: H01L23/538 ,  H01L25/065

CPC classification number: H01L23/5384 ,  H01L25/0655 ,  H01L23/5386

Abstract: An electronic package is provided. The electronic package includes a semiconductor substrate. The semiconductor substrate includes a first active region and a first passive region separated from the first active region. The first active region is configured to regulate a power signal. The first passive region is configured to transmit a data signal.

公开(公告)号：US20210265231A1

公开(公告)日：2021-08-26

申请号：US16799751

申请日：2020-02-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien Lin CHANG CHIEN ,  Chiu-Wen LEE ,  Hung-Jung TU ,  Chang Chi LEE ,  Chin-Li KAO

IPC: H01L23/367 ,  H01L23/48 ,  H01L23/00 ,  H01L21/48

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first die, a second die, and a thermal dissipation element. The first die has a first surface. The second die is disposed on the first surface. The thermal dissipation element is disposed on the first surface. The thermal dissipation element includes a first portion extending in a first direction substantially parallel to the first surface and partially covered by the second die and a second portion extending in a second direction substantially perpendicular to the first surface to be adjacent to an edge of the second die.

公开(公告)号：US20170263589A1

公开(公告)日：2017-09-14

申请号：US15416907

申请日：2017-01-26

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien Lin CHANG CHIEN ,  Chang Chi LEE ,  Chin-Li KAO ,  Dao-Long CHEN ,  Ta-Chien CHENG

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L21/78 ,  H01L23/31 ,  H01L23/367

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3672 ,  H01L24/33 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2225/06589

Abstract: A semiconductor device package includes a package substrate, a first electronic device, a second electronic device and a first molding layer. The package substrate includes a first surface, a second surface opposite to the first surface, and an edge. The first electronic device is positioned over and electrically connected to the package substrate through the first surface. The second electronic device is positioned over and electrically connected to the first electronic device. The first molding layer is positioned over the package substrate, and the first molding layer encapsulates a portion of the first surface and the edge of the package substrate.