公开(公告)号：US10049942B2

公开(公告)日：2018-08-14

申请号：US14853373

申请日：2015-09-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony I. Chou ,  Judson R. Holt ,  Arvind Kumar ,  Henry K. Utomo

IPC: H01L21/265 ,  H01L21/266 ,  H01L29/167 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L27/092

Abstract: An aspect of the disclosure provides for an asymmetric semiconductor device. The asymmetric semiconductor device may comprise: a substrate; and a fin-shaped field effect transistor (FINFET) disposed on the substrate, the FINFET including: a set of fins disposed proximate a gate; a first epitaxial region disposed on a source region on the set of fins, the first epitaxial region having a first height; and a second epitaxial region disposed on a drain region on the set of fins, the second epitaxial region having a second height, wherein the first height is distinct from the second height.

公开(公告)号：US20180190768A1

公开(公告)日：2018-07-05

申请号：US15848591

申请日：2017-12-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dina H. Triyoso ,  Timothy J. McArdle ,  Judson R. Holt ,  Amy L. Child ,  George R. Mulfinger

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/76264 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/7842 ,  H01L29/7846 ,  H01L29/78684

Abstract: A pFET includes a semiconductor-on-insulator (SOI) substrate; and a trench isolation within the SOI substrate, the trench isolation including a raised portion extending above an upper surface of the SOI substrate. A compressive channel silicon germanium (cSiGe) layer is over the SOI substrate. A strain retention member is positioned between at least a portion of the raised portion of the trench isolation and the compressive cSiGe layer. A gate and source/drain regions are positioned over the compressive cSiGe layer.

公开(公告)号：US09812453B1

公开(公告)日：2017-11-07

申请号：US15431334

申请日：2017-02-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George R. Mulfinger ,  Lakshmanan H. Vanamurthy ,  Scott Beasor ,  Timothy J. McArdle ,  Judson R. Holt ,  Hao Zhang

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/285 ,  H01L21/02 ,  H01L29/66 ,  H01L29/45 ,  H01L29/167 ,  H01L29/165 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/456 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7848

Abstract: A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include forming a Si fin in a PFET region and a pair of Si fins in a NFET region; forming epitaxial S/D regions; forming a spacer over the S/D region in the PFET region; forming a sacrificial cap over the S/D regions in the NFET region, merging the pair of Si fins; removing the spacer from the S/D region in the PFET region; forming silicide trenches over the S/D regions in the PFET and NEFT regions; implanting dopant into the S/D region in the PFET region while the sacrificial cap protects the S/D regions in the NFET region; removing the sacrificial cap; and forming a metal layer over top surfaces of the S/D region in the PFET region and top and bottom surfaces of the S/D regions in the NFET region.

公开(公告)号：US09722045B2

公开(公告)日：2017-08-01

申请号：US14921434

申请日：2015-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bhupesh Chandra ,  Viorel Ontalus ,  Timothy J. McArdle ,  Paul Chang ,  Claude Ortolland ,  Judson R. Holt

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/225

CPC classification number: H01L29/66575 ,  H01L21/2254 ,  H01L21/2257 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/785

Abstract: The disclosure relates to semiconductor structures and, more particularly, to one or more devices with an engineered layer for modulating voltage threshold (Vt) and methods of manufacture. The method includes finding correlation of thickness of a buffer layer to out-diffusion of dopant into extension regions during annealing of a doped layer formed on the buffer layer. The method further includes determining a predetermined thickness of the buffer layer to adjust device performance characteristics based on the correlation of thickness of the buffer layer to the out-diffusion. The method further includes forming the buffer layer adjacent to gate structures to the predetermined thickness.

公开(公告)号：US09698226B1

公开(公告)日：2017-07-04

申请号：US15095376

申请日：2016-04-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Timothy J. McArdle ,  Judson R. Holt ,  Junli Wang

IPC: H01L29/04 ,  H01L29/161 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/161 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/04 ,  H01L29/045 ,  H01L29/10 ,  H01L29/1054 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: Semiconductor device fabrication method and structures are provided having a substrate structure which includes a silicon layer at an upper portion. The silicon layer is recessed in a first region of the substrate structure and remains unrecessed in a second region of the substrate structure. A protective layer having a first germanium concentration is formed above the recessed silicon layer in the first region, which extends along a sidewall of the unrecessed silicon layer of the second region. A semiconductor layer having a second germanium concentration is disposed above the protective layer in the first region of the substrate structure, where the first germanium concentration of the protective layer inhibits lateral diffusion of the second germanium concentration from the semiconductor layer in the first region into the unrecessed silicon layer in the second region of the substrate structure.

公开(公告)号：US20170179257A1

公开(公告)日：2017-06-22

申请号：US15453939

申请日：2017-03-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony I. Chou ,  Judson R. Holt ,  Arvind Kumar ,  Henry K. Utomo

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L21/306 ,  H01L29/165 ,  H01L21/84 ,  H01L29/10

CPC classification number: H01L29/66636 ,  H01L21/30604 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/786

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a partially depleted semiconductor-on-insulator (SOI) junction isolation structure using a nonuniform trench shape formed by reactive ion etching (RIE) and crystallographic wet etching. The nonuniform trench shape may reduce back channel leakage by providing an effective channel directly below a gate stack having a width that is less than a width of an effective back channel directly above the isolation layer.

公开(公告)号：US20160181359A1

公开(公告)日：2016-06-23

申请号：US14578523

申请日：2014-12-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. Holt ,  Shogo Mochizuki ,  Alexander Reznicek ,  Melissa A. Smith

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/304 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065

CPC classification number: H01L21/02639 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02636 ,  H01L21/02647 ,  H01L21/2022 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/7605 ,  H01L21/76248 ,  H01L21/76294 ,  H01L29/0642 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/785

Abstract: A semiconductor structure including: trench-defining layer; an epitaxial layer; and a set of defect-blocking member(s). The trench-defining layer includes a trench surface which defines an elongated interior space called the “trench.” The epitaxial layer is grown epitaxially in the interior space of the trench. Each defect blocking member of the set of defect blocking members: (i) extends from a portion of trench surface into the interior space of the trench; and (ii) is located below a top surface of the epitaxial layer. The defect blocking member(s) are designed to arrest the propagation of generally-longitudinal defects in the epitaxial layer, as it is grown, where the generally-longitudinal defects are defects that propagate at least generally in the elongation direction of the trench.

Abstract translation: 一种半导体结构，包括：沟槽限定层; 外延层; 和一组缺陷阻挡构件。 沟槽限定层包括限定被称为“沟槽”的细长内部空间的沟槽表面。外延层在沟槽的内部空间中外延生长。 该组缺陷阻挡构件的每个缺陷阻挡构件：（i）从沟槽表面的一部分延伸到沟槽的内部空间中; 和（ii）位于外延层的顶表面下方。 缺陷阻挡构件设计成在其生长时阻止外延层中的大致纵向缺陷的传播，其中大致纵向缺陷是至少大体上在沟槽的伸长方向上传播的缺陷。

公开(公告)号：US09236477B2

公开(公告)日：2016-01-12

申请号：US14181832

申请日：2014-02-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jack O. Chu ,  Christos Dimitrakopoulos ,  Eric C. Harley ,  Judson R. Holt ,  Timothy J. McArdle ,  Matthew W. Stoker

IPC: H01L29/78 ,  H01L29/16 ,  H01L21/02 ,  H01L21/324 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L21/0243 ,  H01L21/02447 ,  H01L21/02527 ,  H01L21/02612 ,  H01L21/02639 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/66037 ,  H01L29/66795 ,  H01L29/7781

Abstract: Silicon-carbon alloy structures can be formed as inverted U-shaped structures around semiconductor fins by a selective epitaxy process. A planarization dielectric layer is formed to fill gaps among the silicon-carbon alloy structures. After planarization, remaining vertical portions of the silicon-carbon alloy structures constitute silicon-carbon alloy fins, which can have sublithographic widths. The semiconductor fins may be replaced with replacement dielectric material fins. In one embodiment, employing a patterned mask layer, sidewalls of the silicon-carbon alloy fins can be removed around end portions of each silicon-carbon alloy fin. An anneal is performed to covert surface portions of the silicon-carbon alloy fins into graphene layers. In one embodiment, each graphene layer can include only a horizontal portion in a channel region, and include a horizontal portion and sidewall portions in source and drain regions. If a patterned mask layer is not employed, each graphene layer can include only a horizontal portion.

Abstract translation: 硅碳合金结构可以通过选择性外延工艺形成为围绕半导体翅片的倒U形结构。 形成平坦化介电层以填充硅 - 碳合金结构之间的间隙。 在平坦化之后，硅 - 碳合金结构的剩余垂直部分构成可以具有亚光刻宽度的硅碳合金翅片。 半导体翅片可以用替换的介质材料翅片代替。 在一个实施例中，采用图案化掩模层，可以在每个硅 - 碳合金散热片的端部周围除去硅 - 碳合金散热片的侧壁。 执行退火以将硅碳合金翅片的表面部分隐藏成石墨烯层。 在一个实施例中，每个石墨烯层可以仅包括沟道区域中的水平部分，并且在源极和漏极区域中包括水平部分和侧壁部分。 如果不使用图案化掩模层，则每个石墨烯层可以仅包括水平部分。

公开(公告)号：US20190043944A1

公开(公告)日：2019-02-07

申请号：US15667376

申请日：2017-08-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Matthew W. Stoker ,  Judson R. Holt ,  Timothy J. McArdle ,  Annie Lévesque

IPC: H01L29/06 ,  H01L27/108 ,  H01L21/02 ,  H01L29/49 ,  H01L29/423

Abstract: At least one method, apparatus and system disclosed herein involves forming increased surface regions within EPI structures. A fin on a semiconductor substrate is formed. On a top portion of the fin, an epitaxial (EPI) structure is formed. The EPI structure has a first EPI portion having a first material and a second EPI portion having a second material. The first and second EPI portions are separated by a first separation layer. A first cavity is formed within the EPI structure by removing a portion of the second material in the second portion. A first conductive material is deposited into the first cavity.

公开(公告)号：US09536985B2

公开(公告)日：2017-01-03

申请号：US14499356

申请日：2014-09-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Brian J. Greene ,  Eric C. T. Harley ,  Judson R. Holt ,  Yue Ke ,  Rishikesh Krishnan ,  Renee T. Mo ,  Yinxiao Yang

IPC: H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/7848

Abstract: A method for producing a semiconductor structure, as well as a semiconductor structure, that uses a partial removal of an insulating layer around a semiconductor fin, and subsequently epitaxially growing an additional semiconductor material in the exposed regions, while maintaining the shape of the fin with the insulating layer.

Abstract translation: 一种用于制造半导体结构的方法以及半导体结构，其使用半导体鳍周围的绝缘层的部分去除，并且随后在暴露区域中外延生长另外的半导体材料，同时保持鳍的形状，同时保持鳍的形状 绝缘层。