公开(公告)号：US10580701B1

公开(公告)日：2020-03-03

申请号：US16168441

申请日：2018-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Scott Beasor ,  Haiting Wang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66

Abstract: A method of forming a gate structure in a gate cavity laterally defined by a sidewall spacer and recessing the sidewall spacer so as to form a recessed sidewall spacer with a recessed upper surface is disclosed. In this example, the method also includes performing at least one etching process to form a tapered upper surface on the exposed portion of the gate structure above the recessed upper surface of the spacer and forming a gate cap above the tapered upper surface of the gate structure and above the recessed upper surface of the recessed sidewall spacer.

公开(公告)号：US10522644B1

公开(公告)日：2019-12-31

申请号：US16014076

申请日：2018-06-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guowei Xu ,  Hui Zang ,  Haiting Wang ,  Scott Beasor

IPC: H01L27/088 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768

Abstract: Various processes form different structures including exemplary apparatuses that include (among other components) a first layer having channel regions, source/drain structures in the first layer on opposite sides of the channel regions, a gate insulator on the channel region, and a gate stack on the gate insulator. The gate stack can include a gate conductor, and a stack insulator or a gate contact on the gate conductor. The gate stack has lower sidewalls adjacent to the source/drain structures and upper sidewalls distal to the source/drain structures. Further, lower spacers are between the source/drain contacts and the lower sidewalls of the gate stack; and upper spacers between the source/drain contacts and the upper sidewalls of the gate stack. In some structures, the upper spacers can partially overlap the lower spacers.

公开(公告)号：US10475890B2

公开(公告)日：2019-11-12

申请号：US15728070

申请日：2017-10-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Wei Zhao ,  Hui Zang ,  Hong Yu ,  Zhenyu Hu ,  Scott Beasor ,  Erik Geiss ,  Jerome Ciavatti ,  Jae Gon Lee

IPC: H01L29/417 ,  H01L27/11 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to scaled memory structures with middle of the line cuts and methods of manufacture The structure comprises: a plurality of fin structures formed on a substrate; a plurality of gate structures spanning over adjacent fin structures; a cut in adjacent epitaxial source/drain regions; and a cut in contact material formed adjacent to the plurality of gate structures, which provides separate contacts.

公开(公告)号：US10403742B2

公开(公告)日：2019-09-03

申请号：US15712748

申请日：2017-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Zhao ,  Haiting Wang ,  David P. Brunco ,  Jiehui Shu ,  Shesh Mani Pandey ,  Jinping Liu ,  Scott Beasor

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/10 ,  H01L21/84 ,  H01L27/12

Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.

公开(公告)号：US10326002B1

公开(公告)日：2019-06-18

申请号：US16004935

申请日：2018-06-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Scott Beasor ,  Zhenyu Hu

IPC: H01L29/02 ,  H01L29/778 ,  H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/417

Abstract: Methods of forming self-aligned gate contacts and cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include self-aligned gate contacts and cross-coupling contacts. A sidewall spacer is formed at a sidewall of a gate structure and an epitaxial semiconductor layer is formed adjacent to the sidewall spacer. After forming the epitaxial semiconductor layer, the sidewall spacer is recessed with a first etching process. After recessing the spacer, the gate structure is recessed with a second etching process. After recessing the gate structure, a cross-coupling contact is formed that connects the gate structure with the epitaxial semiconductor layer.

公开(公告)号：US09330971B2

公开(公告)日：2016-05-03

申请号：US14195932

申请日：2014-03-04

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Scott Beasor ,  Jagar Singh

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/50 ,  H01L27/06 ,  H01L21/8234

CPC classification number: H01L21/76877 ,  H01L21/76802 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5228 ,  H01L27/0629 ,  H01L27/1211 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes etching an ILD layer of dielectric material overlying a semiconductor substrate that includes a device region to form first contact vias that expose active areas of the device region. The ILD layer is etched to form second contact vias that correspondingly expose a gate that is disposed in the device region and a patterned resistive metal-containing layer that is disposed in the ILD layer adjacent to the device region. The first contact vias and the second contact vias are filled with an electrically-conductive material to form first contacts that are in electrical communication with the active areas and second contacts that include a gate contact and a metal resistor contact that are in electrical communication with the gate and the patterned resistive metal-containing layer, respectively.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，制造集成电路的方法包括蚀刻覆盖在半导体衬底上的介电材料的ILD层，其包括器件区域，以形成暴露器件区域的有源区域的第一接触孔。 ILD层被蚀刻以形成相应地暴露设置在器件区域中的栅极的第二接触孔，以及设置在与器件区域相邻的ILD层中的图案化的含电阻金属层。 第一接触通孔和第二接触通孔被填充有导电材料，以形成与有源区和第二接触电连通的第一接触，第二接触包括栅接触和金属电阻接触， 栅极和图案化的含电阻金属层。

公开(公告)号：US20150255335A1

公开(公告)日：2015-09-10

申请号：US14195932

申请日：2014-03-04

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Scott Beasor ,  Jagar Singh

IPC: H01L21/768 ,  H01L49/02 ,  H01L23/50 ,  H01L27/06 ,  H01L23/48

CPC classification number: H01L21/76877 ,  H01L21/76802 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5228 ,  H01L27/0629 ,  H01L27/1211 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes etching an ILD layer of dielectric material overlying a semiconductor substrate that includes a device region to form first contact vias that expose active areas of the device region. The ILD layer is etched to form second contact vias that correspondingly expose a gate that is disposed in the device region and a patterned resistive metal-containing layer that is disposed in the ILD layer adjacent to the device region. The first contact vias and the second contact vias are filled with an electrically-conductive material to form first contacts that are in electrical communication with the active areas and second contacts that include a gate contact and a metal resistor contact that are in electrical communication with the gate and the patterned resistive metal-containing layer, respectively.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，制造集成电路的方法包括蚀刻覆盖在半导体衬底上的介电材料的ILD层，其包括器件区域，以形成暴露器件区域的有源区域的第一接触孔。 ILD层被蚀刻以形成相应地暴露设置在器件区域中的栅极的第二接触孔，以及设置在与器件区域相邻的ILD层中的图案化的含电阻金属层。 第一接触通孔和第二接触通孔被填充有导电材料，以形成与有源区和第二接触电连通的第一接触，第二接触包括栅接触和金属电阻接触， 栅极和图案化的含电阻金属层。

公开(公告)号：US10832965B2

公开(公告)日：2020-11-10

申请号：US15868229

申请日：2018-01-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yiheng Xu ,  Haiting Wang ,  Qun Gao ,  Scott Beasor ,  Kyung Bum Koo ,  Ankur Arya

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/161 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3105

Abstract: Integrated circuit devices include trenches in a material layer that divide the material layer into fins. With such devices, an insulator partially fills the trenches and contacts the material layer. The top surface of the insulator (e.g., the surface opposite where the insulator contacts the material layer) has a convex dome shape between at least two of the fins. The dome shape has a first thickness from (from the bottom of the trench) where the insulator contacts the fins, and a second thickness that is greater than the first thickness where the insulator is between the fins. Further, there is a maximum thickness difference between the first and second thicknesses at the midpoint between the fins (e.g., the highest point of the dome shape is at the midpoint between the fins). Also, the top surface of the first insulator has concave divots where the first insulator contacts the fins.

公开(公告)号：US10818659B2

公开(公告)日：2020-10-27

申请号：US16161294

申请日：2018-10-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Hui Zang ,  Guowei Xu ,  Scott Beasor

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

Abstract: Processes form integrated circuit apparatuses that include parallel fins, wherein the fins are patterned in a first direction, and parallel gate structures intersect the fins in a second direction perpendicular to the first direction. Also, source/drain structures are positioned on the fins between the gate structures, source/drain contacts are positioned on the source/drain structures, sidewall insulators are positioned between the gate structures and the source/drain contacts (wherein the sidewall insulators have a lower portion adjacent to the fins and an upper portion distal to the fins), and upper sidewall spacers are positioned between the upper portion of the sidewall insulators and the source/drain contacts.

公开(公告)号：US10804379B2

公开(公告)日：2020-10-13

申请号：US15980436

申请日：2018-05-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Scott Beasor

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/28

Abstract: A method for producing a finFET to prevent gate contact and trench silicide (TS) electrical shorts. Embodiments include forming a finFET over a substrate, the finFET comprising an epi S/D region formed at sides of a gate; forming an α-Si layer in a recess over the epi S/D; forming an oxide layer over the α-Si layer; forming a non-TS isolation opening over the substrate; forming a low dielectric constant layer in the non-TS isolation opening; removing the oxide layer and α-Si layer; forming an opening over the gate and an opening over the epi S/D region; and forming a gate contact in the opening over the gate and an epi S/D contact over the opening over the epi S/D region.