公开(公告)号：US09929048B1

公开(公告)日：2018-03-27

申请号：US15388400

申请日：2016-12-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Chanro Park ,  Andre Labonte ,  Lars Liebmann

IPC: H01L21/768 ,  H01L21/033 ,  H01L29/66 ,  H01L23/535 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/0332 ,  H01L21/76805 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/535 ,  H01L29/66545

Abstract: Disclosed are methods of forming an integrated circuit (IC) structure with self-aligned middle of the line (MOL) contacts and the resulting IC structure. In the methods, different, selectively etchable, dielectric materials are used above the gate level for: a dielectric cap above a gate; a dielectric spacer above a gate sidewall spacer and laterally surrounding the dielectric cap; and a stack of dielectric layer(s) that covers the dielectric cap, the dielectric spacer, and metal plugs positioned laterally adjacent to the dielectric spacer and above source/drain regions. Due to the different dielectric materials, subsequently formed gate and source/drain contacts are self-aligned in two dimensions to provide protection against the occurrence of opens between wires and/or vias in the first BEOL metal level and the contacts and to further provide protection against the occurrence of shorts between the gate contact and any metal plugs and between the source/drain contacts and the gate.

公开(公告)号：US09824921B1

公开(公告)日：2017-11-21

申请号：US15202817

申请日：2016-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andre Labonte ,  Ruilong Xie ,  Xunyuan Zhang

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L23/535 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/532 ,  H01L29/417

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/823431 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method provides a structure having a FinFET in an Rx region, the FinFET including a channel, source/drain (S/D) regions and a gate, the gate including gate metal. A cap is formed over the gate having a high-k dielectric liner and a core. Trench silicide (TS) is disposed on sides of the gate. The TS is recessed to a level above a level of the gate and below a level of the cap. An oxide layer is disposed over the structure. A CB trench is patterned into the oxide layer within the Rx region to expose the core and liner at an intermediate portion of the CB trench. The core is selectively etched relative to the liner to extend the CB trench to a bottom at the gate metal. The CB trench is metalized to form a CB contact.

公开(公告)号：US09691897B2

公开(公告)日：2017-06-27

申请号：US14867193

申请日：2015-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andre Labonte ,  Andreas Knorr

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/7845 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A three-dimensional transistor includes a semiconductor substrate, a fin coupled to the substrate, the fin including an active region across a top portion thereof, the active region including a source, a drain and a channel region therebetween. The transistor further includes a gate situated above the channel region, and a gate contact situated in the active region, no portion thereof being electrically coupled to the source or drain. The transistor is achieved by removing a portion of the source/drain contact situated beneath the gate contact during fabrication.

公开(公告)号：US20160359009A1

公开(公告)日：2016-12-08

申请号：US14731960

申请日：2015-06-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andre Labonte ,  Andreas Knorr

IPC: H01L29/423 ,  H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/28 ,  H01L23/535 ,  H01L29/78

CPC classification number: H01L29/4232 ,  H01L21/28008 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: One method disclosed herein includes, among other things, forming a gate contact opening in a layer of insulating material, wherein the gate contact opening is positioned at least partially vertically above a active region, the gate contact opening exposing a portion of at least a gate cap layer of a gate structure, performing at least one etching process to remove the gate cap layer and recess a sidewall spacer so as to thereby define a spacer cavity and expose at least an upper surface of a gate electrode within the gate contact opening, filling the spacer cavity with an insulating material while leaving the upper surface of the gate electrode exposed, and forming a conductive gate contact in the gate contact opening.

Abstract translation: 本文公开的一种方法包括在绝缘材料层中形成栅极接触开口，其中栅极接触开口至少部分地垂直于有源区域上方，栅极接触开口暴露至少一个栅极的一部分 盖层，执行至少一个蚀刻工艺以去除栅极盖层并凹陷侧壁间隔件，从而限定间隔件空腔并暴露门接触开口内的至少栅极电极的上表面，填充 在离开栅电极的上表面的情况下，具有绝缘材料的间隔腔暴露，并且在栅极接触开口中形成导电栅极接触。

公开(公告)号：US09455254B2

公开(公告)日：2016-09-27

申请号：US14536243

申请日：2014-11-07

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Andre Labonte ,  Su Chen Fan ,  Balasubramanian S. Pranatharthi Haran

IPC: H01L21/8234 ,  H01L21/768 ,  H01L27/088 ,  H01L29/45 ,  H01L23/528 ,  H01L29/66 ,  H01L21/311 ,  H01L21/283 ,  H01L29/417

CPC classification number: H01L27/088 ,  H01L21/283 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/528 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/66515 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66606 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method disclosed herein includes, among other things, forming a gate cap layer above a recessed final gate structure and above recessed sidewall spacers, forming a recessed trench silicide region that is conductively coupled to the first source/drain region, the recessed trench silicide region having an upper surface that is positioned at a level that is below the recessed upper surface of the sidewall spacers, forming a combined contact opening in at least one layer of material that exposes a conductive portion of the recessed final gate structure and a portion of the trench silicide region, and forming a combined gate and source/drain contact structure in the combined contact opening.

Abstract translation: 本文公开的一种方法包括在凹陷的最终栅极结构上方和在凹陷的侧壁间隔物上方形成栅极盖层，形成导电耦合到第一源极/漏极区域的凹陷沟槽硅化物区域，凹陷沟槽硅化物区域 具有位于所述侧壁间隔物的凹陷的上表面下方的水平面的上表面，在暴露所述凹入的最终栅极结构的导电部分的至少一层材料中形成组合的接触开口， 沟槽硅化物区域，并且在组合的接触开口中形成组合的栅极和源极/漏极接触结构。

公开(公告)号：US20160268415A1

公开(公告)日：2016-09-15

申请号：US15063604

申请日：2016-03-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andre Labonte ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/45

CPC classification number: H01L29/785 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76897 ,  H01L29/45 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative device disclosed herein includes, among other things, a dielectric layer disposed above a source/drain region and a gate structure of a transistor, a first conductive contact positioned in the dielectric layer and contacting the gate structure, wherein a first spacer is disposed on a sidewall of the first conductive contact, and a second conductive contact positioned in the dielectric layer and contacting the source/drain region, wherein the first spacer at least partially defines a spacing between the first conductive contact and the second conductive contact.

Abstract translation: 本文公开的一个示例性器件包括设置在源极/漏极区域和晶体管的栅极结构之上的电介质层，位于电介质层中并接触栅极结构的第一导电接触，其中设置第一间隔物 在所述第一导电接触件的侧壁上，以及定位在所述电介质层中并接触所述源极/漏极区域的第二导电接触件，其中所述第一间隔件至少部分地限定所述第一导电接触件和所述第二导电接触件之间的间隔。