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公开(公告)号：US20180304624A1
公开(公告)日：2018-10-25
申请号：US16024302
申请日：2018-06-29
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Peter James Fricke , Michael W. Cumbie , Scott A. Linn
IPC: B41J2/045
CPC classification number: B41J2/04541 , B41J2/0452 , B41J2/04528 , B41J2/04543 , B41J2/04573 , B41J2/0458 , B41J2/04596 , B41J2/04598 , B41J2202/13 , B41J2202/21
Abstract: A wide array printhead module includes a plurality of printhead die, each of the printhead die includes a number of nozzles. The nozzles form a number of primitives. A nozzle firing heater is coupled to each of the nozzles. An application specific integrated circuit (ASIC) controls a number of activation pluses that activate the nozzle firing heaters for each of the nozzles associated with the primitives. The activation pulses are delayed between each of the primitives via internal delays and external delays to reduce peak power demands of the printhead die. The ASIC determines the internal delays within each printhead die.
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公开(公告)号：US10022962B1
公开(公告)日：2018-07-17
申请号：US15665560
申请日：2017-08-01
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Scott A. Linn , George H. Corrigan, III , Michael W. Cumbie
Abstract: A fluidic die may include a number of actuators. The number of actuators form a number of primitives. The fluidic die may include a digital-to-analog converter (DAC) to drive a number of the delay circuits. The delay circuits delay a number of activation pulses that activate the actuators associated with the primitives to reduce peak power demands of the fluidic die. A number of delay circuits may be coupled to each primitive.
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公开(公告)号：US20180072059A1
公开(公告)日：2018-03-15
申请号：US15822348
申请日：2017-11-27
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Peter J. Fricke , Andrew L. Van Brocklin , Scott A. Linn
CPC classification number: B41J2/14209 , B41J2/04541 , B41J2/04573 , B41J2/04581 , B41J2/04588 , B41J2/0459 , B41J2/14072 , B41J2/14201 , B41J2/155 , B41J2002/14491 , B41J2202/20
Abstract: In some examples, a piezoelectric fluid ejection assembly includes a micro-electro mechanical system (MEMS) die including a plurality of nozzles, a first application-specific integrated circuit (ASIC) die electrically connected to the MEMS die, and a second ASIC die electrically connected to the MEMS die. The first ASIC die includes a plurality of driver amplifiers for respective nozzles of a first number of the plurality of nozzles, and a plurality of unique waveform data generators to generate respective different waveforms for activating the nozzles of the first number of the plurality of nozzles.
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公开(公告)号：US20160375691A1
公开(公告)日：2016-12-29
申请号：US15230010
申请日：2016-08-05
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Andrew L. Van Brocklin , Paul A. Liebert , Adam L. Ghozeil , Scott A. Linn
IPC: B41J2/175
CPC classification number: B41J2/17566 , B41J2/0451 , B41J2/04555 , B41J2/0458 , B41J2/125 , B41J2/14153 , B41J2002/17579
Abstract: In an embodiment, a fluid level sensor includes a sensor plate and a current source. The fluid level sensor also includes an algorithm to bias the current source such that current applied to the sensor plate induces a maximum difference in response voltage between a dry sensor plate condition and a wet sensor plate condition.
Abstract translation: 在一个实施例中，液位传感器包括传感器板和电流源。 液位传感器还包括用于偏置电流源的算法，使得施加到传感器板的电流在干传感器板条件和湿传感器板状况之间引起响应电压的最大差异。
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公开(公告)号：US12240245B2
公开(公告)日：2025-03-04
申请号：US16977675
申请日：2018-12-03
Applicant: Hewlett-Packard Development Company, L.P.
Inventor： James Michael Gardner , Scott A. Linn , Stephen D. Panshin , Jefferson P. Ward , David Owen Roethig
Abstract: In an example, a logic circuit comprising a communications interface including a data contact to communicate via a communications bus, an enablement contact, separate from the communication interface, to receive an input to enable the logic circuit, and at least one memory register, comprising at least one reconfigurable address register. The logic circuit may be configured, such that, when enabled, it responds to communications sent via the communication bus which are addressed to the address held in a reconfigurable address register.
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Patent Agency Ranking
公开(公告)号：US12183430B2
公开(公告)日：2024-12-31
申请号：US18135697
申请日：2023-04-17
Applicant: Hewlett-Packard Development Company, L.P.
Inventor： Scott A. Linn , James Michael Gardner , Michael W. Cumbie
Abstract: An integrated circuit to drive a number of fluid actuation devices, comprising a circuit configured to have a memory access state which can be set to one of an enabled state and disabled state. The integrated circuit to include a fluid actuation circuit to transmit selection information for a fluid actuation device, the selection information comprising a data state bit. The integrated circuit to include a memory cell array, configured so that each memory cell is accessible by the memory access state being enabled, and the data state bit being set.
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公开(公告)号：US12145360B2
公开(公告)日：2024-11-19
申请号：US18393224
申请日：2023-12-21
Applicant: Hewlett-Packard Development Company, L.P.
Inventor： Scott A. Linn , James Michael Gardner , Michael W. Cumbie
IPC: B41J2/045
Abstract: An integrated circuit includes a plurality of memory cells, an address decoder to select memory cells based on a data signal, activation logic to activate selected memory cells based on the data signal and a fire signal, and configuration logic to enable or disable access to the plurality of memory cells.
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公开(公告)号：US12030312B2
公开(公告)日：2024-07-09
申请号：US18448794
申请日：2023-08-11
Applicant: Hewlett-Packard Development Company, L.P.
Inventor： Boon Bing Ng , James Michael Gardner , Scott A. Linn
CPC classification number: B41J2/04536 , B41J2/04541 , B41J2/04555 , B41J2/04563 , B41J2/0458 , B41J2/04586 , G06F3/1293 , G06F13/1668 , G11C7/1069 , G11C16/10 , G11C16/26 , G11C2207/105
Abstract: A memory circuit for a print component including a plurality of I/O pads, including an analog pad, to connect to a plurality of signal paths which communicate operating signals to the print component. The memory circuit includes a controllable selector connected in line with one of the signal paths via the I/O pads, the selector controllable to disconnect the corresponding signal path to the print component, and a memory component to store memory values associated with the print component. A control circuit, in response to a sequence of operating signals received by the I/O pads representing a memory read, to operate the controllable selector to disconnect the signal path to the print component to block the memory read of the print component, and provide an analog signal to the analog pad to provide an analog electrical value at the analog pad representing stored memory values selected by the memory read.
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29.发明授权公开(公告)号：US11932014B2
公开(公告)日：2024-03-19
申请号：US18139106
申请日：2023-04-25
Applicant: Hewlett-Packard Development Company, L.P.
Inventor： Scott A. Linn , James Michael Gardner , John Rossi
CPC classification number: B41J2/0458 , B41J2/04585 , B41J2002/14475
Abstract: A print component includes an array of fluidic actuation structures including a first column of fluidic actuating structures addressable by a set of actuation addresses, each fluidic actuating structure having a different one of the actuation addresses and having a fluidic architecture type, and a second column of fluidic actuating structures addressable by the set of actuation addresses. Each fluidic actuating structure of the second column has a different one of the actuation addresses and has a same fluidic architecture type as the fluidic actuating structure of the first column having the same address. An address bus communicates the set of addresses to the array of fluidic actuating structures, and a fire signal line communicates a plurality of fire pulse signal types to the array of fluidic actuating structures, the fire pulse signal type depending on the actuation address on the address bus.
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公开(公告)号：US11858265B2
公开(公告)日：2024-01-02
申请号：US17985590
申请日：2022-11-11
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Scott A. Linn , James Michael Gardner , Erik D. Ness
IPC: B41J29/393 , B41J2/045
CPC classification number: B41J2/04541 , B41J2/04543 , B41J2/04586
Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes a plurality of first non-volatile memory cells and control logic. Each first non-volatile memory cell stores a customization bit. The control logic configures an operation of the integrated circuit based on the customization bits.
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