公开(公告)号：US20190306061A1

公开(公告)日：2019-10-03

申请号：US15939532

申请日：2018-03-29

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Gregg B. Lesartre ,  Derek Alan Sherlock ,  Nicholas George McDonald

IPC: H04L12/801 ,  H04L12/825

Abstract: Example implementations relate to congestion management across a network fabric. An example implementation includes setting an uncongested sequence length threshold to a first value. A completed transaction received count may also be set to an initial value. The completed transaction received count may be incremented in response to a completion of a transaction request. In response to a detected congestion event, the injection rate may be decreased. A second value for the uncongested sequence length threshold may be determined from the CTR count, and the uncongested sequence length threshold may be set to the second value. Furthermore, in response to the CTR count being greater than or equal to the uncongested sequence length threshold, the injection rate may be increased.

公开(公告)号：US10409681B2

公开(公告)日：2019-09-10

申请号：US15500067

申请日：2015-01-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Derek Alan Sherlock ,  Harvey Ray

IPC: G06F11/10 ,  G06F11/14 ,  G06F3/06 ,  G06F11/20

Abstract: According to an example, a retransmission sequence involving non-idempotent primitives in a fault-tolerant memory fabric may be modified. For example, a redundancy controller may request a sequence to access a stripe in the fault-tolerant memory fabric, wherein the sequence involves a non-idempotent primitive. In response to determining an expiration of a time threshold for the non-idempotent primitive, the redundancy controller may read other data in other cachelines in the stripe, calculate a new parity value by performing an idempotent exclusive-or primitive on the new data with the other data in the stripe, and write the new parity to the stripe using an idempotent write primitive.

公开(公告)号：US20190065314A1

公开(公告)日：2019-02-28

申请号：US16082262

申请日：2016-03-22

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Derek Alan Sherlock ,  Harvey Ray

IPC: G06F11/10 ,  G06F11/20 ,  G06F3/06

Abstract: A memory device may operate in multiple modes. In a first mode, writes are not committed. In a second mode, writes are committed.

公开(公告)号：US20180217929A1

公开(公告)日：2018-08-02

申请号：US15746618

申请日：2015-07-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Mark David Lillibridge ,  Gary Gostin ,  Paolo Faraboschi ,  Derek Alan Sherlock ,  Harvey Ray

IPC: G06F12/06 ,  G06F3/06

CPC classification number: G06F12/0607 ,  G06F3/0611 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2212/1016 ,  G06F2212/1024

Abstract: In some examples, each processor of a plurality of processors applies an interleave transform to perform interleaved access of a plurality of memory banks, where for any given memory address in use by the plurality of processors, applying any of the interleave transforms results in selection of a same memory bank of the plurality of memory banks and a same address within the same memory bank.

公开(公告)号：US20170185343A1

公开(公告)日：2017-06-29

申请号：US15314710

申请日：2014-09-02

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Harvey Ray ,  Gary Gostin ,  Derek Alan Sherlock ,  Gregg B. Lesartre

IPC: G06F3/06

Abstract: According to an example, a lock may be requested by a first redundancy controller from a parity media controller to perform a first sequence that accesses multiple memory modules in a stripe. The lock may be acquired for the stripe so that the first sequence may be performed on the stripe. The lock may then be released from the stripe.

公开(公告)号：US11775443B2

公开(公告)日：2023-10-03

申请号：US15323700

申请日：2014-10-23

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Derek Alan Sherlock

IPC: G06F12/1027 ,  G06F11/07 ,  G06F12/14 ,  G06F12/1009 ,  G06F12/1081

CPC classification number: G06F12/1027 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/1009 ,  G06F12/1081 ,  G06F12/145 ,  G06F12/1466 ,  G06F2212/1052 ,  G06F2212/651 ,  G06F2212/657 ,  G06F2212/681 ,  G06F2212/684

Abstract: A system includes a central processing unit (CPU) to process data with respect to a virtual address generated by the CPU. A first memory management unit (MMU) translates the virtual address to a physical address of a memory with respect to the data processed by the CPU. A supervisory MMU translates the physical address of the first MMU to a storage address for storage and retrieval of the data in the memory. The supervisory MMU controls access to the memory via the storage address generated by the first MMU.

公开(公告)号：US20200278807A1

公开(公告)日：2020-09-03

申请号：US15929725

申请日：2020-05-18

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Derek Alan Sherlock

IPC: G06F3/06 ,  G06F13/16 ,  G06F12/02

Abstract: In some examples, a tracker receives a write request that is acknowledged upon receipt by a destination media controller without waiting for achievement of persistence of write data associated with the write request. The tracker adds an identifier of the destination media controller to a tracking structure in response to the identifier not already being present in the tracking structure. The tracker sends a request to persist write operations to media controllers identified by the tracking structure.

公开(公告)号：US10740233B2

公开(公告)日：2020-08-11

申请号：US15768557

申请日：2015-10-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Derek Alan Sherlock

IPC: G06F12/00 ,  G06F12/0804 ,  G06F12/126

Abstract: According to an example, cache operations may be managed by detecting that a cacheline in a cache is being dirtied, determining a current epoch number, in which the current epoch number is associated with a store operation and wherein the epoch number is incremented each time a thread of execution completes a flush-barrier checkpoint, and inserting an association of the cacheline to the current epoch number into a field of the cacheline that is being dirtied.

公开(公告)号：US10691348B2

公开(公告)日：2020-06-23

申请号：US16274189

申请日：2019-02-12

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Derek Alan Sherlock ,  Shawn Walker

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06

Abstract: A system comprises a processor, a memory fabric, and a fabric bridge coupled to the memory fabric and the processor. The fabric bridge may receive, from the processor a first eviction request comprising first eviction data, transmit, to the processor, a message indicating the fabric bridge has accepted the first eviction request, transmit a first write comprising the first eviction data to the fabric, receive, from the processor, a second eviction request comprising second eviction data, and transmit a second write comprising the second eviction data to the fabric. Responsive to transmitting the second write request, the fabric bridge may transmit, to the processor, a message indicating the fabric bridge accepted the second eviction request, determine that the first write and the second write have persisted, and transmit, to the processor, a notification to the processor responsive to determining that the first write and the second write have persisted.

公开(公告)号：US10664369B2

公开(公告)日：2020-05-26

申请号：US15500063

申请日：2015-01-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Derek Alan Sherlock ,  Harvey Ray ,  Michael Kontz

IPC: G06F11/20 ,  G06F11/07 ,  G06F11/10

Abstract: According to an example, a failed component in a fault-tolerant memory fabric may be determined by transmitting request packets along a plurality of routes between the redundancy controller and a media controller in periodic cycles. The redundancy controller may determine whether route failures for all of the plurality of routes have occurred within a number of consecutive periodic cycles. In response to determining that route failures for all of the plurality of routes have occurred within a number of consecutive periodic cycles, the media controller is established as failed. In response to determining that route failures for less than all of the plurality of routes have occurred within the number of consecutive periodic cycles, a fabric device is established as failed.