-
公开(公告)号：US20080249774A1
公开(公告)日：2008-10-09
申请号：US12061156
申请日：2008-04-02
Applicant: Hyun-Soo KIM , Myeong-gi Jeong , Hyun-Sik Shim , Young-Hee Park , Ha-Jin Yoo , Guen-Chang Kwak , Hye-Jin Kim , Kyung-Sook Bae
Inventor： Hyun-Soo KIM , Myeong-gi Jeong , Hyun-Sik Shim , Young-Hee Park , Ha-Jin Yoo , Guen-Chang Kwak , Hye-Jin Kim , Kyung-Sook Bae
IPC: G10L17/00
CPC classification number: G10L17/02
Abstract: Disclosed is a method for speech speaker recognition of a speech speaker recognition apparatus, the method including detecting effective speech data from input speech; extracting an acoustic feature from the speech data; generating an acoustic feature transformation matrix from the speech data according to each of Principal Component Analysis (PCA) and Linear Discriminant Analysis (LDA), mixing each of the acoustic feature transformation matrixes to construct a hybrid acoustic feature transformation matrix, and multiplying the matrix representing the acoustic feature with the hybrid acoustic feature transformation matrix to generate a final feature vector; and generating a speaker model from the final feature vector, comparing a pre-stored universal speaker model with the generated speaker model to identify the speaker, and verifying the identified speaker.
Abstract translation: 公开了一种语音讲话者识别装置的语音说话人识别方法，该方法包括从输入语音中检测有效的语音数据; 从所述语音数据中提取声学特征; 根据主成分分析（PCA）和线性判别分析（LDA）中的每一个从语音数据生成声学特征变换矩阵，混合每个声学特征变换矩阵以构建混合声学特征变换矩阵，并将表示 声学特征与混合声学特征变换矩阵以产生最终特征向量; 以及从所述最终特征向量生成扬声器模型，将预先存储的通用扬声器模型与所产生的扬声器模型进行比较以识别所述扬声器，以及验证所识别的扬声器。
-
公开(公告)号：US20080112220A1
公开(公告)日：2008-05-15
申请号：US11984145
申请日：2007-11-14
Applicant: Kwang-jin Lee , Won-Seok Lee , Qi Wang , Hye-Jin Kim , Joon Yong Choi
Inventor： Kwang-jin Lee , Won-Seok Lee , Qi Wang , Hye-Jin Kim , Joon Yong Choi
CPC classification number: G11C7/1078 , G11C7/1084 , G11C7/225 , G11C16/10
Abstract: A non-volatile semiconductor memory device may include a memory cell array that may include a plurality of memory transistors; a input circuit that may control a voltage level of an internal reference voltage and a delay time of an internal clock signal in response to an MRS trim code or an electric fuse trim code, and that may generate a first buffered input signal; a column gate that may gate the first buffered input signal in response to a decoded column address signal; and a sense amplifier that may amplify an output signal of the memory cell array to output to the column gate, and that may receive an output signal of the column gate to output to the memory cell array. The non-volatile semiconductor memory device may properly buffer an input signal of a small swing range.
Abstract translation: 非易失性半导体存储器件可以包括可以包括多个存储晶体管的存储单元阵列; 输入电路，其可以响应于MRS修剪代码或电熔丝修剪代码来控制内部参考电压的电压电平和内部时钟信号的延迟时间，并且可以产生第一缓冲输入信号; 列门，其可以响应于解码列地址信号而选通第一缓冲输入信号; 以及读出放大器，其可以放大存储单元阵列的输出信号以输出到列门，并且可以接收列门的输出信号以输出到存储器单元阵列。 非易失性半导体存储器件可以适当地缓冲小摆动范围的输入信号。
-
公开(公告)号：US20060120569A1
公开(公告)日：2006-06-08
申请号：US11291607
申请日：2005-11-30
Applicant: Do-Hyung Kim , Jae-Yeon Lee , Su-Young Chi , Ho-Sub Yoon , Kye-Kyung Kim , Soo-Hyun Cho , Hye-Jin Kim , Young-Jo Cho
Inventor： Do-Hyung Kim , Jae-Yeon Lee , Su-Young Chi , Ho-Sub Yoon , Kye-Kyung Kim , Soo-Hyun Cho , Hye-Jin Kim , Young-Jo Cho
CPC classification number: G06K9/00362
Abstract: A user recognizing system and method is provided. According to the user recognizing system and method, user ID and predetermined user feature information are stored, first and second user feature information are extracted from the user image data transmitted from the image input unit, and first and second probabilities that the extracted first and second user feature information determine the predetermined user are respectively generated based on the information stored at the user information database, the first user feature information being absolutely unique biometric information and the second user feature information being unique semibiometric information under a predetermined condition, and ID of the input image is finally determined by combining the first probability and the second probability. According to the user recognizing system and method, a user identity can be authenticated even when the user freely moves.
-
24.发明授权Non-volatile memory device using variable resistance element with an improved write performance 有权使用可变电阻元件的非易失性存储器件具有改进的写入性能公开(公告)号：US08964488B2
公开(公告)日：2015-02-24
申请号：US13470617
申请日：2012-05-14
Applicant: Hye-Jin Kim , Kwang-Jin Lee , Du-Eung Kim , Hung-Jun An
Inventor： Hye-Jin Kim , Kwang-Jin Lee , Du-Eung Kim , Hung-Jun An
CPC classification number: G11C5/14 , G11C7/1078 , G11C7/1096 , G11C8/10 , G11C11/22 , G11C13/00 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0038 , G11C13/0069 , G11C2013/0088 , G11C2013/009 , G11C2213/72
Abstract: A non-volatile memory device using a variable resistive element is provided. The non-volatile memory device includes a memory cell array having a plurality of non-volatile memory cells, a first voltage generator configured to generate a first voltage, a voltage pad configured to receive an external voltage that has a level higher than the first voltage, a write driver configured to be supplied with the external voltage and configured to write data to the plurality of non-volatile memory cells selected from the memory cell array; a sense amplifier configured to be supplied with the external voltage and configured to read data from the plurality of non-volatile memory cells selected from the memory cell array, and a row decoder and a column decoder configured to select the plurality of non-volatile memory cells included in the memory cell array, the row decoder being supplied with the first voltage and the column decoder being supplied with the external voltage.
Abstract translation: 提供了使用可变电阻元件的非易失性存储器件。 非易失性存储器件包括具有多个非易失性存储器单元的存储单元阵列，被配置为产生第一电压的第一电压发生器，被配置为接收具有高于第一电压的电平的外部电压的电压焊盘 写入驱动器，被配置为被提供有所述外部电压并被配置为向从所述存储单元阵列中选择的所述多个非易失性存储器单元写入数据; 感测放大器，被配置为被提供有外部电压并且被配置为从从存储单元阵列中选择的多个非易失性存储器单元读取数据;行解码器和列解码器，被配置为选择多个非易失性存储器 包括在存储单元阵列中的单元，行解码器被提供有第一电压，并且列解码器被提供有外部电压。
-
25.发明授权Non-volatile memory device generating a reset pulse based on a set pulse, and method of operating the same 有权基于设定脉冲产生复位脉冲的非易失性存储器件及其操作方法公开(公告)号：US08787100B2
公开(公告)日：2014-07-22
申请号：US13710504
申请日：2012-12-11
Applicant: Yong Jin Kwon , Kwang Jin Lee , Hye-Jin Kim
Inventor： Yong Jin Kwon , Kwang Jin Lee , Hye-Jin Kim
CPC classification number: G11C7/22 , G11C13/00 , G11C13/0004 , G11C13/0061 , G11C13/0069 , G11C29/021 , G11C29/023 , G11C29/028 , G11C2013/0088
Abstract: A non-volatile memory device includes a set pulse generator configured to generate a set pulse, a reset pulse generator configured to generate a reset pulse based on the set pulse, and a write driver block configured to write second data to a second non-volatile memory cell using the reset pulse, while writing first data to a first non-volatile memory cell using the set pulse.
Abstract translation: 非易失性存储器件包括被配置为产生置位脉冲的置位脉冲发生器，被配置为基于所设置的脉冲产生复位脉冲的复位脉冲发生器，以及被配置为将第二数据写入第二非易失性的写入驱动器块 使用复位脉冲的存储单元，同时使用设定脉冲将第一数据写入第一非易失性存储单元。
-
Patent Agency Ranking
公开(公告)号：US08189422B2
公开(公告)日：2012-05-29
申请号：US12929123
申请日：2011-01-03
Applicant: Kwang Jin Lee , Joon Min Park , Hye-Jin Kim
Inventor： Kwang Jin Lee , Joon Min Park , Hye-Jin Kim
IPC: G11C8/00
CPC classification number: G11C13/0069 , G11C7/22 , G11C8/12 , G11C13/0004 , G11C2013/0076 , G11C2207/2209
Abstract: A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a memory bank accessed by a write address during the write operation is the same as a memory bank accessed by a read address during the read operation, the semiconductor device may suspend the write operation automatically or in response to an internal signal until the read operation is finished and performs the write operation after the read operation is finished.
Abstract translation: 根据示例实施例的半导体器件可以被配置为使得当执行写入操作时输入用于执行读取操作的读取命令，并且当在写入操作期间由写入地址访问的存储体组与 存储体在读取操作期间由读取地址访问，半导体器件可以自动暂停写入操作或响应于内部信号直到读取操作完成，并且在读取操作完成之后执行写入操作。
-
27.发明授权公开(公告)号：US08159867B2
公开(公告)日：2012-04-17
申请号：US12395999
申请日：2009-03-02
Applicant: Woo-Yeong Cho , Kwang-Jin Lee , Hye-Jin Kim
Inventor： Woo-Yeong Cho , Kwang-Jin Lee , Hye-Jin Kim
IPC: G11C11/00
CPC classification number: G11C8/10 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C2013/0076 , G11C2013/0078
Abstract: A phase change memory device performs a program operation by receiving program data to be programmed in selected memory cells, sensing read data already stored in the selected memory cells by detecting respective magnitudes of verify currents flowing through the selected memory cells when a verify read voltage is applied to the selected memory cells, determining whether the read data is identical to the program data, and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, programming the one or more selected memory cells with the program data.
Abstract translation: 相变存储器件通过接收在所选择的存储器单元中被编程的程序数据来执行编程操作，当检验读取电压为检测电压时，通过检测流过选择的存储器单元的检验电流的大小来感测已经存储在所选存储单元中的读取数据 应用于所选择的存储单元，确定读取的数据是否与程序数据相同，并且在确定所选择的存储单元中的一个或多个的程序数据与相应的读取数据不相同时，编程所选择的一个或多个 存储单元与程序数据。
-
公开(公告)号：US08098518B2
公开(公告)日：2012-01-17
申请号：US12476875
申请日：2009-06-02
Applicant: Hye-Jin Kim , Byung-Gil Choi , Du-Eung Kim
Inventor： Hye-Jin Kim , Byung-Gil Choi , Du-Eung Kim
IPC: G11C11/00
CPC classification number: G11C13/0023 , G11C8/10 , G11C13/00 , G11C13/0004 , G11C13/0026
Abstract: A nonvolatile memory device may include a memory cell array with a plurality of nonvolatile memory cells arranged in an array of rows and columns. Each of a plurality of bit lines may be coupled to nonvolatile memory cells in a respective one of the columns of the array, and each of a plurality of column selection switches may be coupled to a respective one of the bit lines. A column decoder may be coupled to the plurality of column selection switches, and the column decoder may be configured to select a first one of the bit lines using a first column selection signal having a first signal level applied to a first one of the column selection switches. The column decoder may be further configured to select a second one of the bit lines using a second column selection signal having a second signal level applied to a second one of the column selection switches with the second signal level being different than the first signal level.
Abstract translation: 非易失性存储器件可以包括具有排列成行和列阵列的多个非易失性存储单元的存储单元阵列。 多个位线中的每一个可以耦合到阵列的各个列中的非易失性存储器单元，并且多个列选择开关中的每一个可以耦合到相应的一个位线。 列解码器可以耦合到多个列选择开关，并且列解码器可以被配置为使用具有施加到列选择中的第一个的第一信号电平的第一列选择信号来选择位线中的第一位 开关。 列解码器还可以被配置为使用具有第二信号电平的第二列选择信号来选择位线中的第二位，其中第二信号电平施加到第二信号电平不同于第一信号电平的列选择开关中的第二信号电平。
-
公开(公告)号：US20100061146A1
公开(公告)日：2010-03-11
申请号：US12556787
申请日：2009-09-10
Applicant: Byung-Gil Choi , Hye-Jin Kim
Inventor： Byung-Gil Choi , Hye-Jin Kim
CPC classification number: G11C8/08 , G11C13/0004 , G11C13/0028 , G11C2213/72
Abstract: A nonvolatile memory device may include a memory cell array having a plurality of nonvolatile memory cells arranged in a matrix including a plurality of rows of the nonvolatile memory cells. Each of a plurality of word lines may be coupled with nonvolatile memory cells of a respective row of the matrix. A row decoder may be coupled to the plurality of word lines with the row decoder being configured to disable at least one of the word lines using a row bias having a level that is adjusted responsive to changes in temperature. Such a nonvolatile memory device may operate with reduced standby currents.
Abstract translation: 非易失性存储器件可以包括存储单元阵列，该存储单元阵列具有以矩阵形式布置的多个非易失性存储单元，包括多行非易失性存储单元。 多个字线中的每一个可以与矩阵的相应行的非易失性存储器单元耦合。 行解码器可以耦合到多个字线，其中行解码器被配置为使用具有响应于温度变化来调整的电平的行偏置来禁用至少一个字线。 这种非易失性存储器件可以以减少的待机电流工作。
-
公开(公告)号：US20090296459A1
公开(公告)日：2009-12-03
申请号：US12476875
申请日：2009-06-02
Applicant: Hye-Jin Kim , Byung-Gil Choi , Du-Eung Kim
Inventor： Hye-Jin Kim , Byung-Gil Choi , Du-Eung Kim
CPC classification number: G11C13/0023 , G11C8/10 , G11C13/00 , G11C13/0004 , G11C13/0026
Abstract: A nonvolatile memory device may include a memory cell array with a plurality of nonvolatile memory cells arranged in an array of rows and columns. Each of a plurality of bit lines may be coupled to nonvolatile memory cells in a respective one of the columns of the array, and each of a plurality of column selection switches may be coupled to a respective one of the bit lines. A column decoder may be coupled to the plurality of column selection switches, and the column decoder may be configured to select a first one of the bit lines using a first column selection signal having a first signal level applied to a first one of the column selection switches. The column decoder may be further configured to select a second one of the bit lines using a second column selection signal having a second signal level applied to a second one of the column selection switches with the second signal level being different than the first signal level.
Abstract translation: 非易失性存储器件可以包括具有排列成行和列阵列的多个非易失性存储单元的存储单元阵列。 多个位线中的每一个可以耦合到阵列的各个列中的非易失性存储器单元，并且多个列选择开关中的每一个可以耦合到相应的一个位线。 列解码器可以耦合到多个列选择开关，并且列解码器可以被配置为使用具有施加到列选择中的第一个的第一信号电平的第一列选择信号来选择位线中的第一位 开关。 列解码器还可以被配置为使用具有第二信号电平的第二列选择信号来选择位线中的第二位，其中第二信号电平施加到第二信号电平不同于第一信号电平的列选择开关中的第二信号电平。
-
-
-
-
-
-
-
-
-
Search Results
58
records
(took 0.023 seconds)
