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公开(公告)号:US11257182B2
公开(公告)日:2022-02-22
申请号:US16943984
申请日:2020-07-30
Applicant: Intel Corporation
Inventor: John Gierach , Abhishek Venkatesh , Travis Schluessler , Devan Burke , Tomer Bar-On , Michael Apodaca
Abstract: Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.
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公开(公告)号:US11244479B2
公开(公告)日:2022-02-08
申请号:US16919839
申请日:2020-07-02
Applicant: Intel Corporation
Inventor: Karthik Vaidyanathan , Prasoonkumar Surti , Hugues Labbe , Atsuo Kuwahara , Sameer KP , Jonathan Kennedy , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh
Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.
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公开(公告)号:US11030713B2
公开(公告)日:2021-06-08
申请号:US15483829
申请日:2017-04-10
Applicant: Intel Corporation
Inventor: Karthik Vaidyanathan , Prasoonkumar Surti , Michael Apodaca , Murali Ramadoss , Abhishek Venkatesh , Joydeep Ray , Abhishek R. Appu
IPC: G06T1/60 , G06T9/00 , H04N19/503 , H04N19/436
Abstract: An embodiment of a graphics apparatus may include an embedded local memory, and a memory extender communicatively coupled to the embedded local memory to extend the embedded local memory. The memory extender may be configured to compress information and store the compressed information in the embedded local memory. Additionally, or alternatively, the memory extender may be configured to expose the embedded local memory for non-local access. Other embodiments are disclosed and claimed.
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公开(公告)号:US20210097639A1
公开(公告)日:2021-04-01
申请号:US16583478
申请日:2019-09-26
Applicant: Intel Corporation
Inventor: Abhishek Venkatesh , Selvakumar Panneer
Abstract: Embodiments described herein are generally directed to conservative rasterization pipeline configurations that allow EarlyZ to be enabled for conservative rasterization. An embodiment of a method includes receiving, by a conservative rasterizer, a primitive; creating, by the conservative rasterizer, a pixel location stream based on the primitive and inner coverage data for each pixel within the pixel location stream indicative of whether the corresponding pixel is fully covered or partially covered by the primitive; for each block of pixels of the pixel location stream, launching, by the conservative rasterizer, a thread of a pixel shader, including causing EarlyZ to be performed or not for fully covered pixels and partially covered pixels, respectively; and generating, by the pixel shader, a stream of pixel updates by conditionally processing the pixel location stream to incorporate pixel shading characteristics, including for partially covered pixels computing a depth value and causing LateZ to be performed.
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25.
公开(公告)号:US20200211511A1
公开(公告)日:2020-07-02
申请号:US16723337
申请日:2019-12-20
Applicant: Intel Corporation
Inventor: Travis Schluessler , Abhishek Venkatesh , John Gierach , Tomer Bar-On , Devan Burke
IPC: G09G5/36 , G09G5/391 , G06T15/40 , G06T15/20 , G06T7/70 , G06T15/00 , G09G3/00 , G06T1/20 , G09G5/00
Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.
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26.
公开(公告)号:US20200074714A1
公开(公告)日:2020-03-05
申请号:US16566989
申请日:2019-09-11
Applicant: Intel Corporation
Inventor: Michael Apodaca , Prasoonkumar Surti , Karthik Vaidyanathan , Murali Ramadoss , Abhishek Venkatesh , Jonathan Kennedy , Slawomir Grajewski
Abstract: A computing system to obtain an output includes a multi-plane rendering module includes a renderer receives a plurality of graphical objects to generate one or more image planes of object data, a resampler upscales lower resolution image planes to a higher resolution used by the output image, and a rasterizer combine pixels from a common location in the plurality of image planes after each image plane is upsampled to the higher resolution. The renderer receives one of the graphical objects having a location value along a z-axis of the scene, determines which of a plurality of image planes the graphical objects is located using the z-axis location for the graphical object, each of the planes possess a corresponding image resolution, and renders the graphical object into the image plane at the image resolution corresponding determined image plane.
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公开(公告)号:US10540260B2
公开(公告)日:2020-01-21
申请号:US15903393
申请日:2018-02-23
Applicant: Intel Corporation
Inventor: Travis Schluessler , Abhishek Venkatesh , Elmoustapha Ould-Ahmed-Vall , John Gierach , Tomer Bar On , Devan Burke
Abstract: In one example, an apparatus comprises processing circuitry to analyze a program at compile time to determine a set of latency parameters associated with instruction sets implemented to execute the program and select a latency management technique based at least in part on the set of latency parameters associated with instruction sets implemented to execute the program. Other examples may be described and claimed.
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公开(公告)号:US10522113B2
公开(公告)日:2019-12-31
申请号:US15858486
申请日:2017-12-29
Applicant: Intel Corporation
Inventor: Travis Schluessler , Abhishek Venkatesh , John Gierach , Tomer Bar-On , Devan Burke
IPC: G06T15/40 , G09G5/36 , G09G5/391 , G06T15/20 , G06T7/70 , G06T15/00 , G09G3/00 , G06T1/20 , G09G5/00 , G06T3/00 , G09G5/397 , G06T1/60 , G06F3/14 , G09G5/377
Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.
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公开(公告)号:US20190259128A1
公开(公告)日:2019-08-22
申请号:US16256441
申请日:2019-01-24
Applicant: Intel Corporation
Inventor: Abhishek Venkatesh , Prasoonkumar Surti , Slawomir Grajewski , Louis Feng , Kai Xiao , Tomasz Janczak , Devan Burke , Travis T. Schluessler
Abstract: An embodiment of a graphics apparatus may include a tile candidate identifier to determine if a compute kernel is a tile candidate, and a compute kernel tiler communicatively coupled to the tile candidate identifier to tile the compute kernel if the compute kernel is determined to be a tile candidate. Other embodiments are disclosed and claimed.
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公开(公告)号:US20190205736A1
公开(公告)日:2019-07-04
申请号:US15858014
申请日:2017-12-29
Applicant: Intel Corporation
Inventor: Amit Bleiweiss , Abhishek Venkatesh , Gokce Keskin , John Gierach , Oguz Elibol , Tomer Bar-On , Huma Abidi , Devan Burke , Jaikrishnan Menon , Eriko Nurvitadhi , Pruthvi Gowda Thorehosur Appajigowda , Travis T. Schluessler , Dhawal Srivastava , Nishant Patel , Anil Thomas
CPC classification number: G06N3/063 , G06F9/3887 , G06N3/04 , G06N3/08 , G06N5/046 , G06N20/00 , G06T1/20
Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a at least one processor to perform operations to implement a neural network and compute logic to accelerate neural network computations.
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