公开(公告)号：US20190206780A1

公开(公告)日：2019-07-04

申请号：US15857238

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Prithwish Chatterjee ,  Junnan Zhao ,  Sai Vadlamani ,  Ying Wang ,  Rahul Jain ,  Andrew J. Brown ,  Lauren A. Link ,  Cheng Xu ,  Sheng C. Li

IPC: H01L23/498 ,  H01F27/28 ,  H01L21/48 ,  H01F41/04 ,  H01L25/16

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/49816

Abstract: Methods/structures of forming in-package inductor structures are described. Embodiments include a substrate including a dielectric material, the substrate having a first side and a second side. A conductive trace is located within the dielectric material. A first layer is on a first side of the conductive trace, wherein the first layer comprises an electroplated magnetic material, and wherein a sidewall of the first layer is adjacent the dielectric material. A second layer is on a second side of the conductive trace, wherein the second layer comprises the electroplated magnetic material, and wherein a sidewall of the second layer is adjacent the dielectric material.

公开(公告)号：US11894282B2

公开(公告)日：2024-02-06

申请号：US16446538

申请日：2019-06-19

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Sergio Antonio Chan Arguedas ,  Peng Li ,  Chandra Mohan Jha ,  Aravindha R. Antoniswamy ,  Cheng Xu ,  Junnan Zhao ,  Ying Wang

IPC: H01L23/367 ,  H01L23/433 ,  H01L23/498 ,  H01L23/053

CPC classification number: H01L23/3675 ,  H01L23/053 ,  H01L23/433 ,  H01L23/49816

Abstract: Disclosed herein are vented lids for integrated circuit (IC) packages, as well as related methods and devices. For example, in some embodiments, an IC package may include a package substrate, a lid, and a die between the package substrate and the lid. A vent may extend between the interior surface and the exterior surface of the lid, and the vent may at least partially overlap the die.

公开(公告)号：US11651885B2

公开(公告)日：2023-05-16

申请号：US16637006

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Junnan Zhao ,  Ying Wang ,  Cheng Xu ,  Kyu Oh Lee ,  Sheng Li ,  Yikang Deng

IPC: H01F17/00 ,  H01F27/255

CPC classification number: H01F17/0013 ,  H01F27/255 ,  H01F2017/002 ,  H01F2017/0066

Abstract: Described herein are magnetic core inductors (MCI) and methods for manufacturing magnetic core inductors. A first embodiment of the MCI can be a snake-configuration MCI. The snake-configuration MCI can be formed by creating an opening in a base material, such as copper, and providing a nonconductive magnetic material in the opening. The inductor can be further formed by forming plated through holes into the core material. The conductive elements for the inductor can be formed in the plated through holes. The nonconductive magnetic material surrounds each conductive element and plated through hole. In embodiments, a layered coil inductor can be formed by drilling a laminate to form a cavity through the laminate within the metal rings of the layered coil inductor. The nonconductive magnetic material can be provided in the cavity.

公开(公告)号：US11557579B2

公开(公告)日：2023-01-17

申请号：US17129269

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Chong Zhang ,  Cheng Xu ,  Junnan Zhao ,  Ying Wang ,  Meizi Jiao

IPC: H01L23/48 ,  H01L25/16 ,  H01L23/538 ,  H01L49/02 ,  H01L23/498 ,  H01L21/56 ,  H01L23/528

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.

公开(公告)号：US11502017B2

公开(公告)日：2022-11-15

申请号：US16215237

申请日：2018-12-10

Applicant: INTEL CORPORATION

Inventor： Cheng Xu ,  Zhimin Wan ,  Lingtao Liu ,  Yikang Deng ,  Junnan Zhao ,  Chandra Mohan Jha ,  Kyu-oh Lee

IPC: H01L23/367 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: An integrated circuit (IC) package comprises a substrate comprising a dielectric and a thermal conduit that is embedded within the dielectric. The thermal conduit has a length that extends laterally within the dielectric from a first end to a second end. An IC die is thermally coupled to the first end of the thermal conduit. The IC die comprises an interconnect that is coupled to the first end of the thermal conduit. An integrated heat spreader comprises a lid over the IC die and at least one sidewall extending from the edge of the lid to the substrate that is thermally coupled to the second end of the thermal conduit.

公开(公告)号：US11482471B2

公开(公告)日：2022-10-25

申请号：US16287728

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Junnan Zhao ,  Zhimin Wan ,  Ying Wang ,  Yikang Deng ,  Chong Zhang ,  Jiwei Sun ,  Zhenguo Jiang ,  Kyu-Oh Lee

IPC: H01L23/46 ,  H01L23/467 ,  H05K1/18 ,  H05K1/02 ,  H05K3/32 ,  H01L23/473 ,  H01L23/66 ,  H01L23/31

Abstract: An integrated circuit package may be formed having a heat transfer fluid chamber, wherein the heat transfer fluid chamber may be positioned to allow a heat transfer fluid to directly contact an integrated circuit device within the integrated circuit package. In one embodiment, a first surface of the integrated circuit device may be electrically attached to a first substrate. The first substrate may then may be electrically attached to a second substrate, such that the integrated circuit device is between the first substrate and the second substrate. The second substrate may include a cavity, wherein the heat transfer fluid chamber may be formed between a second surface of the integrated circuit device and the cavity of the second substrate. Thus, at least a portion of a second surface of the integrated circuit device is exposed to the heat transfer fluid which flows into the heat transfer fluid chamber.

公开(公告)号：US11417614B2

公开(公告)日：2022-08-16

申请号：US15938114

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Kyu-Oh Lee ,  Junnan Zhao ,  Rahul Jain ,  Ji Yong Park ,  Sai Vadlamani ,  Seo Young Kim

IPC: H01L23/64 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.

公开(公告)号：US11387224B2

公开(公告)日：2022-07-12

申请号：US16158186

申请日：2018-10-11

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Zhimin Wan ,  Yikang Deng ,  Junnan Zhao ,  Chong Zhang ,  Chandra Mohan M Jha ,  Ying Wang ,  Kyu-oh Lee

IPC: H01L23/34 ,  H01L25/18 ,  H01L23/00 ,  H01L23/538 ,  F28D20/02

Abstract: A semiconductor device package structure is provided. The semiconductor device package structure includes a substrate having a cavity, and phase change material within the cavity. In an example, the phase change material has a phase change temperature lower than 120 degree centigrade. A die may be coupled to the substrate. In an example, the semiconductor device package structure includes one or more interconnect structures that are to couple the die to the phase change material within the cavity.

公开(公告)号：US11217534B2

公开(公告)日：2022-01-04

申请号：US16646932

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Junnan Zhao ,  Ji Yong Park ,  Kyu Oh Lee

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L23/498

Abstract: Techniques of protecting cored or coreless semiconductor packages having materials formed from dissimilar metals from galvanic corrosion are described. An exemplary semiconductor package comprises one or more build-up layers; first and second semiconductor components (e.g., die, EMIB, etc.) on or embedded in the one or more build-up layers. The first semiconductor component may be electrically coupled to the second semiconductor component via a contact pad and an interconnect structure that are formed in the one or more build-up layers. The contact pad can comprise a contact region, a non-contact region, and a gap region that separates the contact region from the non-contact region. Coupling of the contact pad and an interconnect structure is performed by coupling only the contact region with the interconnect structure. Also, a surface area of the contact region can be designed to substantially equal to a surface area of the interconnect structure.

公开(公告)号：US11031360B2

公开(公告)日：2021-06-08

申请号：US16990782

申请日：2020-08-11

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Yikang Deng ,  Kyu Oh Lee ,  Ji Yong Park ,  Srinivas Pietambaram ,  Ying Wang ,  Chong Zhang ,  Rui Zhang ,  Junnan Zhao

IPC: H01L23/64 ,  H05K1/16 ,  H01L23/522 ,  H01L23/528 ,  H01F27/24 ,  H01L27/04 ,  H01F27/28 ,  H01L21/822

Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connectors can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.