公开(公告)号：US20200211974A1

公开(公告)日：2020-07-02

申请号：US16232524

申请日：2018-12-26

Applicant: Intel Corporation

Inventor： Noriyuki SATO ,  Kevin LIN ,  Kevin O'BRIEN ,  Hui Jae YOO

IPC: H01L23/532 ,  H01L43/10 ,  H01L43/12 ,  H01L21/768 ,  H01L23/522

Abstract: A multilayer conductive line is disclosed. The multilayer conductive line includes a dielectric layer, a Ta barrier layer on the dielectric layer and a superlattice on the Ta barrier layer. The superlattice includes a plurality of interleaved ferromagnetic and non-ferromagnetic material.

公开(公告)号：US20200027827A1

公开(公告)日：2020-01-23

申请号：US16337889

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Manish CHANDHOK

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532

Abstract: Systems and methods for maskless gap (for example, air gap) integration into multilayer interconnects having one or more interconnect lines (for example, metal interconnect lines) embedded in a dielectric layer of the interconnects are described. In various embodiments, the described systems and methods may serve to reduce electrical shorting between adjacent vias in the interconnects. In one embodiment, a spacer layer may be provided to mask portions of an interlayer dielectric (ILD) in the interconnect. These masked portions of the ILD can protect regions between adjacent interconnect lines (for example, metal interconnect lines) from electrical shorting during subsequent metal layer depositions, for example, during a fabrication sequence of the interconnects. Further, the vias may enclose a gap (for example, an air gap) without the need for additional masking steps. Further, such gaps may be inherently self-aligned to the vias and/or spacer layers. Moreover, the gaps may act to reduce capacitance and thereby increase the performance (circuit timing, power consumption, etc.) of the interconnect.

公开(公告)号：US20200006427A1

公开(公告)日：2020-01-02

申请号：US16024684

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Noriyuki SATO ,  Kevin O'BRIEN ,  Eungnak HAN ,  Manish CHANDHOK ,  Gurpreet SINGH ,  Nafees KABIR ,  Kevin LIN ,  Rami HOURANI ,  Abhishek SHARMA ,  Hui Jae YOO

IPC: H01L27/24 ,  H01L45/00

Abstract: An integrated circuit structure includes a first material block comprising a first block insulator layer and a first multilayer stack on the first block insulator layer, the first multilayer stack comprising interleaved pillar electrodes and insulator layers. A second material block is stacked on the first material block and comprises a second block insulator layer, and a second multilayer stack on the second block insulator layer, the second multilayer stack comprising interleaved pillar electrodes and insulator layers. At least one pillar extends through the first material block and the second material block, wherein the at least one pillar has a top width at a top of the first and second material blocks that is greater than a bottom width at a bottom of the first and second material blocks.

公开(公告)号：US20200006261A1

公开(公告)日：2020-01-02

申请号：US16024675

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Kevin LIN

IPC: H01L23/66 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/311 ,  H01L49/02

Abstract: An integrated circuit structure comprises one or more sets of first and second conductive lines along a same direction in an interlayer dielectric (ILD), the first and second conductive lines having a width greater than 2 μm. An air gap is in the ILD between the first and second conductive lines, the air gap extending across the ILD to sidewalls of the first and second conductive lines.

公开(公告)号：US20190393036A1

公开(公告)日：2019-12-26

申请号：US16013842

申请日：2018-06-20

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Charles WALLACE

IPC: H01L21/033 ,  H01L21/3213 ,  H01L21/285

Abstract: Metal spacer-based approaches for fabricating conductive lines/interconnects are described. In an example, an integrated circuit structure includes a substrate. A first spacer pattern is on the substrate, the first spacer pattern comprising a first plurality of dielectric spacers and a first plurality of metal spacers formed along sidewalls of the first plurality of dielectric spacers, wherein the first plurality of dielectric spacers have a first width (W1). A second spacer pattern is on the substrate, where the second spacer pattern interleaved with the first spacer pattern, the second spacer pattern comprising a second plurality of dielectric spacers having a second width (W2) formed on exposed sidewalls of the first plurality of metal spacers, and a second plurality of metal spacers formed on exposed sidewalls of the second plurality of dielectric spacers.

公开(公告)号：US20190355665A1

公开(公告)日：2019-11-21

申请号：US15985561

申请日：2018-05-21

Applicant: Intel Corporation

Inventor： Ehren MANNEBACH ,  Kevin LIN ,  Richard VREELAND

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522

Abstract: Embodiments include an interconnect structure and methods of forming an interconnect structure. In an embodiment, the interconnect structure comprises a semiconductor substrate and an interlayer dielectric (ILD) over the semiconductor substrate. In an embodiment, an interconnect layer is formed over the ILD. In an embodiment, the interconnect layer comprises a first interconnect and a second interconnect. In an embodiment the interconnect structure comprises an electrically insulating plug that separates the first interconnect and the second interconnect. In an embodiment an uppermost surface of the electrically insulating plug is above an uppermost surface of the interconnect layer.

公开(公告)号：US20190287813A1

公开(公告)日：2019-09-19

申请号：US16435240

申请日：2019-06-07

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Robert Lindsey BRISTOL ,  Alan M. MYERS

IPC: H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L21/033

Abstract: Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmasks. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.

公开(公告)号：US20180204797A1

公开(公告)日：2018-07-19

申请号：US15575808

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Robert Lindsey BRISTOL ,  James M. BLACKWELL ,  Rami HOURANI

IPC: H01L23/522 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/02282 ,  H01L21/31144 ,  H01L21/321 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/53209 ,  H01L23/53295

Abstract: Embodiments of the invention include an interconnect structure with a via and methods of forming such structures. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD). A first interconnect line and a second interconnect line extend into the first ILD. According to an embodiment, a second ILD is positioned over the first interconnect line and the second interconnect line. A via may extend through the second ILD and electrically coupled to the first interconnect line. Additionally, embodiments of the invention include a portion of a bottom surface of the via being positioned over the second interconnect line. However, an isolation layer may be positioned between the bottom surface of the via and a top surface of the second interconnect line, according to an embodiment of the invention.

公开(公告)号：US20180145035A1

公开(公告)日：2018-05-24

申请号：US15574816

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Kanwal Jit SINGH ,  Kevin LIN ,  Robert Lindsey BRISTOL

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L21/764 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/49827 ,  H01L23/5222 ,  H01L23/5226 ,  H01L29/0649 ,  H01L2221/1042 ,  H01L2221/1047

Abstract: Embodiments of the invention include interconnect layers with floating interconnect lines and methods of forming such interconnect layers. In an embodiment, a plurality of openings are formed in a first sacrificial material layer. Conductive vias and dielectric pillars may be formed in the openings. A second sacrificial material layer may then be formed over the pillars, the vias, and the first sacrificial material layer. In an embodiment, a permeable etchstop layer is formed over a top surface of the second sacrificial layer. Embodiments then include forming an interconnect line in the second sacrificial material layer. In an embodiment, the first and second sacrificial material layers are removed through the permeable etchstop layer after the interconnect line has been formed. According to an embodiment, the permeable etchstop layer may then be stuffed with a fill material in order to harden the permeable etchstop layer.