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    MULTI-CHIP PACKAGE WITH HIGH DENSITY INTERCONNECTS
    23.
    发明申请
    MULTI-CHIP PACKAGE WITH HIGH DENSITY INTERCONNECTS 审中-公开

    公开(公告)号：US20200321281A1

    公开(公告)日：2020-10-08

    申请号：US16904363

    申请日：2020-06-17

    Applicant: Intel Corporation

    Inventor： Aleksandar Aleksov ,  Adel A. Elsherbini ,  Kristof Darmawikarta ,  Robert A. May ,  Sri Ranga Sai Boyapati

    IPC: H01L23/538 ,  H01L25/18 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L23/498

    Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.

    Multi-chip package with high density interconnects
    24.
    发明授权
    Multi-chip package with high density interconnects 有权

    公开(公告)号：US10727185B2

    公开(公告)日：2020-07-28

    申请号：US16329644

    申请日：2016-09-30

    Applicant: Intel Corporation

    Inventor： Aleksandar Aleksov ,  Adel A. Elsherbini ,  Kristof Darmawikarta ,  Robert A. May ,  Sri Ranga Sai Boyapati

    IPC: H01L23/34 ,  H01L23/538 ,  H01L25/18 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L23/498 ,  H01L21/56

    Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.

    SUBSTRATE EMBEDDED HEAT PIPE
    25.
    发明申请
    SUBSTRATE EMBEDDED HEAT PIPE 审中-公开

    公开(公告)号：US20200176355A1

    公开(公告)日：2020-06-04

    申请号：US16209861

    申请日：2018-12-04

    Applicant: Intel Corporation

    Inventor： Robert A. May ,  Kristof Darmawikarta ,  Rahul Jain ,  Lilia May ,  Maroun Moussallem ,  Prithwish Chatterjee

    IPC: H01L23/473 ,  H01L23/373 ,  H05K7/20

    Abstract: A semiconductor device package structure is provided, which includes a substrate, one or more dies coupled to the substrate, and a heat pipe device. In an example, the heat pipe device may include a conduit that is at least partially embedded within the substrate. The heat pipe device may have a first region coupled to the one or more dies. In an example, the conduit may include a first path for flow of vapor from the first region to an opposing second region. The conduit may further include a second path for flow of liquid from the second region to the first region.

    Polarization defined zero misalignment vias for semiconductor packaging
    26.
    发明授权
    Polarization defined zero misalignment vias for semiconductor packaging 有权

    公开(公告)号：US10453812B2

    公开(公告)日：2019-10-22

    申请号：US15855961

    申请日：2017-12-27

    Applicant: Intel Corporation

    Inventor： Hiroki Tanaka ,  Aleksandar Aleksov ,  Sri Ranga Sai Boyapati ,  Robert A. May ,  Kristof Darmawikarta

    IPC: H01L23/00 ,  H01L23/485 ,  H01L21/027

    Abstract: Techniques that can assist with fabricating a semiconductor package that includes a zero misalignment-via (ZMV) and/or a trace formed using a polarization process are described. The disclosed techniques can result in creation of ZMVs and/or traces between the ZMVs using a process comprising application of polarized light to one or more resist layers (e.g., a photoresist layer, etc.). One embodiment of a technique includes modulating an intensity of light applied to one or more resist layers by interaction of a light source with a photomask and at least one polarizer such that one or more patterns are created on the one or more resist layers. One embodiment of another technique includes creating patterns on one or more resist layers with different types of polarized light formed from a photomask and at least one polarizer. The disclosed techniques can assist with reducing manufacturing costs, reducing development time, and increasing I/O density.

    POLARIZATION DEFINED ZERO MISALIGNMENT VIAS FOR SEMICONDUCTOR PACKAGING
    29.
    发明申请
    POLARIZATION DEFINED ZERO MISALIGNMENT VIAS FOR SEMICONDUCTOR PACKAGING 审中-公开

    公开(公告)号：US20190198467A1

    公开(公告)日：2019-06-27

    申请号：US15855961

    申请日：2017-12-27

    Applicant: Intel Corporation

    Inventor： Hiroki Tanaka ,  Aleksandar Aleksov ,  Sri Ranga Sai Boyapati ,  Robert A. May ,  Kristof Darmawikarta

    IPC: H01L23/00 ,  H01L23/485 ,  H01L21/027

    Abstract: Techniques that can assist with fabricating a semiconductor package that includes a zero misalignment-via (ZMV) and/or a trace formed using a polarization process are described. The disclosed techniques can result in creation of ZMVs and/or traces between the ZMVs using a process comprising application of polarized light to one or more resist layers (e.g., a photoresist layer, etc.). One embodiment of a technique includes modulating an intensity of light applied to one or more resist layers by interaction of a light source with a photomask and at least one polarizer such that one or more patterns are created on the one or more resist layers. One embodiment of another technique includes creating patterns on one or more resist layers with different types of polarized light formed from a photomask and at least one polarizer. The disclosed techniques can assist with reducing manufacturing costs, reducing development time, and increasing I/O density.

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