Hierarchical Mantissa Bit Length Selection for Hardware Implementation of Deep Neural Network

    公开(公告)号:US20190236436A1

    公开(公告)日:2019-08-01

    申请号:US16180250

    申请日:2018-11-05

    Abstract: Hierarchical methods for selecting fixed point number formats with reduced mantissa bit lengths for representing values input to, and/or output, from, the layers of a DNN. The methods begin with one or more initial fixed point number formats for each layer. The layers are divided into subsets of layers and the mantissa bit lengths of the fixed point number formats are iteratively reduced from the initial fixed point number formats on a per subset basis. If a reduction causes the output error of the DNN to exceed an error threshold, then the reduction is discarded, and no more reductions are made to the layers of the subset. Otherwise a further reduction is made to the fixed point number formats for the layers in that subset. Once no further reductions can be made to any of the subsets the method is repeated for continually increasing numbers of subsets until a predetermined number of layers per subset is achieved.

    Hardware Implementation of a Deep Neural Network with Variable Output Data Format

    公开(公告)号:US20190087718A1

    公开(公告)日:2019-03-21

    申请号:US16136553

    申请日:2018-09-20

    Abstract: Hardware implementations of DNNs and related methods with a variable output data format. Specifically, in the hardware implementations and methods described herein the hardware implementation is configured to perform one or more hardware passes to implement a DNN wherein during each hardware pass the hardware implementation receives input data for a particular layer, processes that input data in accordance with the particular layer (and optionally one or more subsequent layers), and outputs the processed data in a desired format based on the layer, or layers, that are processed in the particular hardware pass. In particular, when a hardware implementation receives input data to be processed, the hardware implementation also receives information indicating the desired format for the output data of the hardware pass and the hardware implementation is configured to, prior to outputting the processed data convert the output data to the desired format.

    Relightable texture for use in rendering an image

    公开(公告)号:US10223827B2

    公开(公告)日:2019-03-05

    申请号:US15433211

    申请日:2017-02-15

    Abstract: Relightable free-viewpoint rendering allows a novel view of a scene to be rendered and relit based on multiple views of the scene from multiple camera viewpoints. An initial texture can be segmented into materials and an initial coarse color estimate is determined for each material. Scene geometry is estimated from the captured views of the scene and is used to scale the initial coarse color estimates relative to each other such that the different materials appear to be lit with a similar irradiance. In this way, a global irradiance function is estimated describing the scene illumination. This provides a starting point for a color estimate and shading estimate extraction. The shading estimate can be used to fit surface normals to the global irradiance function. The set of surface normals and the color estimate are stored for subsequent use to allow relighting of the scene.

    Systems and methods for processing images of objects using interpolation between keyframes

    公开(公告)号:US10157446B2

    公开(公告)日:2018-12-18

    申请号:US15335643

    申请日:2016-10-27

    Abstract: An image processing system and method for determining an intrinsic color component of one or more objects present in a sequence of frames, for use in rendering the object(s), are described. Some of the frames of the sequence are to be used as lighting keyframes. A lighting estimate for a lighting keyframe A of the sequence of frames is determined. A lighting estimate for a lighting keyframe B of the sequence of frames is determined. A lighting estimate for an intermediate frame positioned between the lighting keyframes A and B in the sequence is determined by interpolating between the lighting estimates determined for the lighting keyframes A and B of the sequence. The determined lighting estimate for the intermediate frame is used to separate image values representing the object(s) in the intermediate frame into an intrinsic color component and a shading component, for use in rendering the object(s).

    Hardware Implementation of a Convolutional Neural Network

    公开(公告)号:US20170323196A1

    公开(公告)日:2017-11-09

    申请号:US15585571

    申请日:2017-05-03

    Abstract: A method in a hardware implementation of a Convolutional Neural Network (CNN), includes receiving a first subset of data having at least a portion of weight data and at least a portion of input data for a CNN layer and performing, using at least one convolution engine, a convolution of the first subset of data to generate a first partial result; receiving a second subset of data comprising at least a portion of weight data and at least a portion of input data for the CNN layer and performing, using the at least one convolution engine, a convolution of the second subset of data to generate a second partial result; and combining the first partial result and the second partial result to generate at least a portion of convolved data for a layer of the CNN.

    CONVOLUTIONAL NEURAL NETWORK HARDWARE CONFIGURATION

    公开(公告)号:US20250131257A1

    公开(公告)日:2025-04-24

    申请号:US19001166

    申请日:2024-12-24

    Abstract: A method of configuring a hardware implementation of a Convolutional Neural Network (CNN), the method comprising: determining, for each of a plurality of layers of the CNN, a first number format for representing weight values in the layer based upon a distribution of weight values for the layer, the first number format comprising a first integer of a first predetermined bit-length and a first exponent value that is fixed for the layer; determining, for each of a plurality of layers of the CNN, a second number format for representing data values in the layer based upon a distribution of expected data values for the layer, the second number format comprising a second integer of a second predetermined bit-length and a second exponent value that is fixed for the layer; and storing the determined number formats for use in configuring the hardware implementation of a CNN.

    Hierarchical mantissa bit length selection for hardware implementation of deep neural network

    公开(公告)号:US12175349B2

    公开(公告)日:2024-12-24

    申请号:US16180250

    申请日:2018-11-05

    Abstract: Hierarchical methods for selecting fixed point number formats with reduced mantissa bit lengths for representing values input to, and/or output, from, the layers of a DNN. The methods begin with one or more initial fixed point number formats for each layer. The layers are divided into subsets of layers and the mantissa bit lengths of the fixed point number formats are iteratively reduced from the initial fixed point number formats on a per subset basis. If a reduction causes the output error of the DNN to exceed an error threshold, then the reduction is discarded, and no more reductions are made to the layers of the subset. Otherwise a further reduction is made to the fixed point number formats for the layers in that subset. Once no further reductions can be made to any of the subsets the method is repeated for continually increasing numbers of subsets until a predetermined number of layers per subset is achieved.

    Methods and systems for implementing a convolution transpose layer of a neural network

    公开(公告)号:US12174910B2

    公开(公告)日:2024-12-24

    申请号:US18425726

    申请日:2024-01-29

    Abstract: Methods and systems for performing a convolution transpose operation between an input tensor having a plurality of input elements and a filter comprising a plurality of filter weights. The method includes: dividing the filter into a plurality of sub-filters; performing, using hardware logic, a convolution operation between the input tensor and each of the plurality of sub-filters to generate a plurality of sub-output tensors, each sub-output tensor comprising a plurality of output elements; and interleaving, using hardware logic, the output elements of the plurality of sub-output tensors to form a final output tensor for the convolution transpose.

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