公开(公告)号：US09721907B2

公开(公告)日：2017-08-01

申请号：US14945115

申请日：2015-11-18

Applicant: Infineon Technologies AG

Inventor： Helmut Oefner ,  Hans-Joachim Schulze

IPC: H01L29/02 ,  H01L21/302 ,  H01L23/00 ,  H01L21/02 ,  H01L21/304

CPC classification number: H01L23/562 ,  H01L21/02021 ,  H01L21/02035 ,  H01L21/304

Abstract: A wafer that includes a front surface, a back surface, and an edge between the front surface and the back surface having a curved edge profile between an edge of the front surface and a side face of the edge of the wafer. The edge profile includes a first convex curve that joins the edge of the front surface, a second convex curve that joins the side face, and an intermediate concave curve that joins the first convex curve and the second convex curve.

公开(公告)号：US20170103882A1

公开(公告)日：2017-04-13

申请号：US14878362

申请日：2015-10-08

Applicant: Infineon Technologies AG

Inventor： Johannes Freund ,  Helmut Oefner ,  Hans-Joachim Schulze

IPC: H01L21/02 ,  H01L23/544 ,  H01L21/265 ,  H01L21/66

CPC classification number: H01L21/02008 ,  C30B33/00 ,  H01L21/263 ,  H01L21/26533 ,  H01L21/324 ,  H01L22/12 ,  H01L22/20 ,  H01L23/544 ,  H01L2223/54413 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2223/54493

Abstract: An embodiment of a method of manufacturing semiconductor wafers comprises determining at least one material characteristic for at least two positions of a semiconductor ingot. A notch or a flat is formed in a semiconductor ingot extending along an axial direction. A plurality of markings is formed in the semiconductor ingot. At least some of the plurality of markings at different positions along the axial direction are distinguishable from each other by a characteristic feature set depending on the at least one material characteristic. The semiconductor ingot is then sliced into semiconductor wafers.

公开(公告)号：US20160104622A1

公开(公告)日：2016-04-14

申请号：US14867839

申请日：2015-09-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Helmut Oefner ,  Nico Caspary ,  Mohammad Momeni ,  Reinhard Ploss ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze

IPC: H01L21/28 ,  H01L21/322

CPC classification number: H01L29/7393 ,  H01L21/02002 ,  H01L21/02005 ,  H01L21/02008 ,  H01L21/0201 ,  H01L21/02016 ,  H01L21/187 ,  H01L21/2257 ,  H01L21/268 ,  H01L21/28238 ,  H01L21/3221 ,  H01L21/3225 ,  H01L21/324 ,  H01L21/3242 ,  H01L21/76256 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/66325 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813

Abstract: A method for manufacturing a substrate wafer 100 includes providing a device wafer (110) having a first side (111) and a second side (112); subjecting the device wafer (110) to a first high temperature process for reducing the oxygen content of the device wafer (110) at least in a region (112a) at the second side (112); bonding the second side (112) of the device wafer (110) to a first side (121) of a carrier wafer (120) to form a substrate wafer (100); processing the first side (101) of the substrate wafer (100) to reduce the thickness of the device wafer (110); subjecting the substrate wafer (100) to a second high temperature process for reducing the oxygen content at least of the device wafer (110); and at least partially integrating at least one semiconductor component (140) into the device wafer (110) after the second high temperature process.

Abstract translation: 一种用于制造衬底晶片100的方法包括提供具有第一侧面（111）和第二侧面（112）的器件晶片（110）; 至少在第二侧（112）的区域（112a）中对器件晶片（110）进行第一高温工艺以减少器件晶片（110）的氧含量; 将器件晶片（110）的第二侧（112）接合到载体晶片（120）的第一侧（121）以形成衬底晶片（100）; 处理衬底晶片（100）的第一侧（101）以减小器件晶片（110）的厚度; 对所述衬底晶片（100）进行第二高温处理以至少减少所述器件晶片（110）的氧含量; 以及在所述第二高温处理之后至少部分地将至少一个半导体部件（140）集成到所述器件晶片（110）中。

公开(公告)号：US11742215B2

公开(公告)日：2023-08-29

申请号：US17386699

申请日：2021-07-28

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Alexander Breymesser ,  Bernhard Goller ,  Matthias Kuenle ,  Helmut Oefner ,  Francisco Javier Santos Rodriguez ,  Stephan Voss

IPC: H01L21/324 ,  H01L21/78 ,  H01L21/265

CPC classification number: H01L21/3247 ,  H01L21/26506 ,  H01L21/7806

Abstract: A method of forming a semiconductor device, including forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate, increasing the porosity of the first semiconductor layer, first annealing the first semiconductor layer at a temperature of at least 1050° C., forming a second semiconductor layer on the first semiconductor layer and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer.

公开(公告)号：US10957767B2

公开(公告)日：2021-03-23

申请号：US16773225

申请日：2020-01-27

Applicant: Infineon Technologies AG

Inventor： Nico Caspary ,  Helmut Oefner ,  Hans-Joachim Schulze

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/739 ,  H01L29/36 ,  C30B15/04 ,  C30B29/06 ,  C30B30/04 ,  H01L29/167 ,  H01L29/78 ,  H01L29/861

Abstract: A method of manufacturing is provided that includes providing an n-type silicon wafer, the n-type silicon wafer including n-type dopants partially compensated 20% to 80% by p-type dopants, where a net n-type doping concentration of the n-type silicon wafer is in a range from 1×1013 cm−3 to 1×1015 cm−3; forming hydrogen related donors in the n-type silicon wafer by irradiating the n-type silicon wafer with protons; and annealing the n-type silicon wafer after forming the hydrogen related donors.

公开(公告)号：US20200224326A1

公开(公告)日：2020-07-16

申请号：US16830603

申请日：2020-03-26

Applicant: Infineon Technologies AG

Inventor： Johannes Freund ,  Thomas Wuebben ,  Helmut Oefner ,  Hans-Joachim Schulze

IPC: C30B15/04 ,  B28D5/00 ,  C30B15/02 ,  H01L29/739 ,  C30B15/10 ,  C30B29/06 ,  C30B33/00 ,  B28D5/04 ,  H01L21/66 ,  H01L29/66

Abstract: One example describes a method of manufacturing Czochralski (CZ) silicon wafers. The method includes slicing an n-type CZ silicon ingot to form a plurality of CZ silicon wafers, determining a boron concentration of each CZ silicon wafer, dividing the CZ silicon wafers into sub-groups based on the boron concentration, wherein an average value of the boron concentration differs among the sub-groups, and labeling each sub-group of CZ silicon wafers with a different label which is indicative of the boron concentration.

公开(公告)号：US20180350612A1

公开(公告)日：2018-12-06

申请号：US15609438

申请日：2017-05-31

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Helmut Oefner ,  Roland Rupp

IPC: H01L21/3065 ,  H01L21/67 ,  H01L21/02 ,  C30B25/18 ,  C30B31/22 ,  C30B33/12 ,  H01L29/16

CPC classification number: H01L21/3065 ,  C30B25/186 ,  C30B31/22 ,  C30B33/12 ,  H01L21/02074 ,  H01L21/02433 ,  H01L21/02658 ,  H01L21/67075 ,  H01L29/16

Abstract: A method of planarizing a roughened surface of a SiC substrate includes: forming a sacrificial material on the roughened surface of the SiC substrate, the sacrificial material having a density between 35% and 120% of the density of the SiC substrate; implanting ions through the sacrificial material and into the roughened surface of the SiC substrate to form an amorphous region in the SiC substrate; and removing the sacrificial material and the amorphous region of the SiC substrate by wet etching.

公开(公告)号：US20180002826A1

公开(公告)日：2018-01-04

申请号：US15636926

申请日：2017-06-29

Applicant: Infineon Technologies AG

Inventor： Johannes Freund ,  Thomas Wuebben ,  Helmut Oefner ,  Hans-Joachim Schulze

IPC: C30B15/04 ,  B28D5/04 ,  H01L21/66 ,  H01L29/66

CPC classification number: C30B15/04 ,  B28D5/00 ,  B28D5/04 ,  C30B15/02 ,  H01L22/14 ,  H01L22/20 ,  H01L29/66325 ,  H01L29/7393

Abstract: In accordance with a method of manufacturing CZ silicon wafers, a parameter of at least two of the CZ silicon wafers is measured. A group of the CZ silicon wafers falling within a tolerance of a target specification is determined. The group of the CZ silicon wafers is divided into sub-groups taking into account the measured parameter. An average value of the parameter of the CZ silicon wafers of each sub-group differs among the sub-groups, and a tolerance of the parameter of the CZ silicon wafers of each sub-group is smaller than a tolerance of the parameter of the target specification. A labeling configured to distinguish between the CZ silicon wafers of different sub-groups is prepared. The CZ silicon wafers falling within the tolerance of the target specification are packaged.

公开(公告)号：US20170170028A1

公开(公告)日：2017-06-15

申请号：US15379243

申请日：2016-12-14

Applicant: Infineon Technologies AG

Inventor： Werner Schustereder ,  Helmut Oefner ,  Hans-Joachim Schulze ,  Sandeep Walia

IPC: H01L21/322 ,  H01L21/02 ,  H01L21/306 ,  H01L21/223

CPC classification number: H01L21/3225 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02598 ,  H01L21/2236 ,  H01L21/26506 ,  H01L21/30604

Abstract: Disclosed is a method for processing a semiconductor wafer. The method includes forming an oxygen containing region in the semiconductor wafer, wherein forming the oxygen containing region includes introducing oxygen via a first surface into the semiconductor wafer. The method further includes creating vacancies at least in the oxygen containing region and annealing at least the oxygen containing region in an annealing process so as to form oxygen precipitates.

公开(公告)号：US09536838B1

公开(公告)日：2017-01-03

申请号：US14821992

申请日：2015-08-10

Applicant: Infineon Technologies AG

Inventor： Johannes Freund ,  Helmut Oefner ,  Hans-Joachim Schulze

IPC: H01L21/78 ,  H01L23/544

CPC classification number: H01L23/544 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2223/54453 ,  H01L2223/54493

Abstract: An embodiment of a method of manufacturing semiconductor wafers comprises forming a notch or a flat in a semiconductor ingot extending along an axial direction. A plurality of markings are formed in the semiconductor ingot. At least some of the plurality of markings at different positions along the axial direction are distinguishable from each other by a characteristic feature. The semiconductor ingot is then sliced into semiconductor wafers.

Abstract translation: 制造半导体晶片的方法的实施例包括在沿轴向延伸的半导体锭中形成切口或平面。 在半导体晶锭中形成多个标记。 沿着轴向的不同位置处的多个标记中的至少一些可通过特征特征彼此区分开。 然后将半导体锭切成半导体晶片。