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公开(公告)号：US10686258B2
公开(公告)日：2020-06-16
申请号：US16121891
申请日：2018-09-05
Applicant: Integrated Device Technology, Inc.
Inventor： Samet Zihir , Tumay Kanar , Naveen Krishna Yanduru
IPC: H01Q21/00 , H01Q21/22 , H01Q21/24 , H01Q3/28 , H03F3/45 , H04B7/06 , H01Q21/06 , H01Q3/40 , H03F3/195 , H03F3/24 , H04B1/401 , H01Q3/36 , H04B1/44 , H01Q1/26 , H01Q3/46 , H01Q21/20
Abstract: An apparatus includes a phased array antenna panel and a plurality of beam former circuits. The phased array antenna panel generally comprises a plurality of antenna elements. The plurality of beam former circuits are each mounted on the phased array antenna panel adjacent to a number of the antenna elements. Each beam former circuit has one or more ports directly coupled to each of the adjacent antenna elements. Each beam former circuit may be configured to generate a plurality of radio-frequency output signals at the ports while in a transmit mode and receive a plurality of radio-frequency input signals at the ports while in a receive mode. Each beam former circuit generally implements a hard-wired address.
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公开(公告)号：US10547120B2
公开(公告)日：2020-01-28
申请号：US16528890
申请日：2019-08-01
Applicant: Integrated Device Technology, Inc.
Inventor： Samet Zihir , Tumay Kanar
IPC: H01Q21/00 , H04B7/06 , H03F3/24 , H04B1/44 , H04B1/401 , H03F3/45 , H03F3/19 , H03F1/56 , H03F3/195 , H03F1/32 , H03H7/48 , H01Q1/22 , H01Q21/06 , H01Q1/52 , H01Q1/48 , H03F1/02 , H01Q19/30 , H01Q3/36 , H01Q3/28 , H04B1/48 , H04B1/18 , H04B1/04 , H03K21/10 , H03F3/68 , H03G3/30
Abstract: An apparatus includes a package and a chip. The package may comprise (i) a plurality of bonding pads, (ii) a plurality of combiner/splitter circuits, and (iii) a plurality of bumps. The bonding pads may be configured to electrically connect the package with a printed circuit board substrate. The combiner/splitter circuits generally connect each of the bonding pads to two respective bumps of the plurality of bumps. The chip is generally disposed in the package. The chip may comprise a plurality of contact pads and a plurality of transceiver channels. Each of the transceiver channels may comprise a radio-frequency input and a radio-frequency output. The radio-frequency input and the radio-frequency output of each transceiver channel are generally connected to respective contact pads of the chip. The respective contact pads of each transceiver channel are generally coupled to a respective bonding pad of the package via the two respective bumps.
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公开(公告)号：US20190372236A1
公开(公告)日：2019-12-05
申请号：US16528890
申请日：2019-08-01
Applicant: Integrated Device Technology, Inc.
Inventor： Samet Zihir , Tumay Kanar
IPC: H01Q21/00 , H03G3/30 , H04B7/06 , H03F3/24 , H04B1/44 , H04B1/401 , H03F3/45 , H03F3/19 , H03F1/56 , H03F3/195 , H03F1/32 , H03H7/48 , H01Q1/22 , H01Q21/06 , H01Q1/52 , H01Q1/48 , H03F1/02 , H01Q19/30 , H01Q3/36 , H01Q3/28 , H04B1/48 , H04B1/18 , H04B1/04 , H03K21/10 , H03F3/68
Abstract: An apparatus includes a package and a chip. The package may comprise (i) a plurality of bonding pads, (ii) a plurality of combiner/splitter circuits, and (iii) a plurality of bumps. The bonding pads may be configured to electrically connect the package with a printed circuit board substrate. The combiner/splitter circuits generally connect each of the bonding pads to two respective bumps of the plurality of bumps. The chip is generally disposed in the package. The chip may comprise a plurality of contact pads and a plurality of transceiver channels. Each of the transceiver channels may comprise a radio-frequency input and a radio-frequency output. The radio-frequency input and the radio-frequency output of each transceiver channel are generally connected to respective contact pads of the chip. The respective contact pads of each transceiver channel are generally coupled to a respective bonding pad of the package via the two respective bumps.
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24.发明申请公开(公告)号：US20190312360A1
公开(公告)日：2019-10-10
申请号：US16449913
申请日：2019-06-24
Applicant: Integrated Device Technology, Inc.
Inventor： Samet Zihir , Tumay Kanar
IPC: H01Q21/22 , H01Q3/28 , H03F3/45 , H01Q21/24 , H03F3/195 , H04B7/06 , H03F3/24 , H01Q3/36 , H01Q1/26 , H01Q3/46 , H01Q21/00 , H01Q21/06 , H01Q21/20
Abstract: An apparatus includes a plurality of transceiver circuits and a plurality of feedback networks. Each of the plurality of transceiver circuits may be coupled to a respective antenna element in a respective group of antenna elements of a phased array antenna. Each of the transceiver circuits generally comprises a power amplifier circuit configured, when operating in a transmit mode, to drive the respective antenna element in the respective group of antenna elements. Each of the plurality of feedback networks may be coupled between an output and an input of a respective power amplifier circuit of a respective transceiver circuit. Each of the feedback networks generally comprises a resistor and a capacitor connected in series. The respective power amplifier circuit with the feedback network generally maintains a power matching condition with load variation associated with the antenna elements of the phased array antenna.
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公开(公告)号：US20190089401A1
公开(公告)日：2019-03-21
申请号：US16130114
申请日：2018-09-13
Applicant: Integrated Device Technology, Inc.
Inventor： Samet Zihir , Tumay Kanar
CPC classification number: H01Q21/0006 , H01Q1/2283 , H01Q1/48 , H01Q1/523 , H01Q1/526 , H01Q3/28 , H01Q3/36 , H01Q19/30 , H01Q21/0025 , H01Q21/062 , H01Q21/065 , H03F1/0211 , H03F1/0261 , H03F1/3282 , H03F1/565 , H03F3/19 , H03F3/195 , H03F3/245 , H03F3/45089 , H03F3/45475 , H03F3/68 , H03F2200/294 , H03F2200/387 , H03F2200/451 , H03G3/3042 , H03H7/487 , H03K21/10 , H04B1/0458 , H04B1/18 , H04B1/401 , H04B1/44 , H04B1/48 , H04B7/0617
Abstract: An apparatus include a package, a chip and a plurality of bumps. The package may include (i) a plurality of bonding pads configured to exchange a plurality of radio-frequency signals with an antenna panel and (ii) a plurality of transmission lines configured to exchange the radio-frequency signals with the bonding pads. Two of the transmission lines may be connected to each of the bonding pads. The chip may be disposed in the package and may include (i) a plurality of transceiver channels configured to exchange the radio-frequency signals with the transmission lines and (ii) a plurality of switches configured to switch the radio-frequency signals to a signal ground. The bumps may be configured to exchange the radio-frequency signals between the transmission lines of the package and the transceiver channels of the chip. The transmission lines, the bumps and the switches may form a plurality of transmit/receive switches.
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Patent Agency Ranking
公开(公告)号：US10063303B1
公开(公告)日：2018-08-28
申请号：US15817909
申请日：2017-11-20
Applicant: Integrated Device Technology, Inc.
Inventor： Samet Zihir , Tumay Kanar , Naveen Krishna Yanduru
CPC classification number: H01Q21/0006 , H01Q1/2283 , H01Q1/48 , H01Q1/523 , H01Q1/526 , H01Q3/28 , H01Q3/36 , H01Q19/30 , H01Q21/0025 , H01Q21/062 , H01Q21/065 , H03F1/0211 , H03F1/0261 , H03F1/3282 , H03F1/565 , H03F3/19 , H03F3/195 , H03F3/245 , H03F3/45089 , H03F3/45475 , H03F3/68 , H03F2200/294 , H03F2200/387 , H03F2200/451 , H03G3/3042 , H03H7/487 , H03K21/10 , H04B1/0458 , H04B1/18 , H04B1/401 , H04B1/44 , H04B1/48 , H04B7/0617
Abstract: An apparatus includes a switching circuit and a plurality of registers. The switching circuit may be configured to generate a plurality of control signals in response to an enable signal. One control signal at a time may be active while the enable signal is in a transfer state. The registers may be configured to (i) buffer a plurality of setting values received from a memory and (ii) present the setting values from a subset of the registers to a plurality of transceiver circuits while a corresponding control signal is active. The setting values may include a plurality of phase values and a plurality of gain values used in the transceiver circuits to steer a radio frequency beam. Each transceiver channel may update the setting values from the registers within a predetermined time after a corresponding control signal becomes active.
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27.发明授权公开(公告)号：US10063274B1
公开(公告)日：2018-08-28
申请号：US15825736
申请日：2017-11-29
Applicant: Integrated Device Technology, Inc.
Inventor： Samet Zihir , Naveen Krishna Yanduru , Tumay Kanar
CPC classification number: H01Q21/0006 , H01Q1/2283 , H01Q1/48 , H01Q1/523 , H01Q1/526 , H01Q3/28 , H01Q3/36 , H01Q19/30 , H01Q21/0025 , H01Q21/062 , H01Q21/065 , H03F1/0211 , H03F1/0261 , H03F1/3282 , H03F1/565 , H03F3/19 , H03F3/195 , H03F3/245 , H03F3/45089 , H03F3/45475 , H03F3/68 , H03F2200/294 , H03F2200/387 , H03F2200/451 , H03G3/3042 , H03H7/487 , H03K21/10 , H04B1/0458 , H04B1/18 , H04B1/401 , H04B1/44 , H04B1/48 , H04B7/0617
Abstract: An apparatus includes an input port, an output port, a common port, a first impedance matching network, a second impedance matching network, a first switch circuit, and a second switch circuit. The first impedance matching network may be coupled between the input port and the common port. The second impedance matching network may be coupled between the common port and the output port. The first switch circuit may be coupled between the input port and a circuit ground potential. The second switch circuit may be coupled between the output port and the circuit ground potential. The first and the second impedance matching networks are asymmetrical.
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公开(公告)号：US11128327B2
公开(公告)日：2021-09-21
申请号：US16558055
申请日：2019-08-31
Applicant: Integrated Device Technology, Inc.
Inventor： Morteza Abbasi , Tumay Kanar , Naveen Krishna Yanduru
Abstract: An apparatus includes a transceiver circuit, a series capacitor, and a shunt switch. The transceiver circuit may comprise a transmit chain including an output matching network and a receive chain including an input matching network. An output of the output matching network may be connected directly to an input/output of the transceiver circuit. The series capacitor may be connected between an input of the input matching network and the output of the output matching network. The shunt switch may be connected between the input of the input matching network and a circuit ground potential of the transceiver circuit.
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公开(公告)号：US10756442B2
公开(公告)日：2020-08-25
申请号：US16128976
申请日：2018-09-12
Applicant: Integrated Device Technology, Inc.
Inventor： Tumay Kanar , Chih-Hsiang Ko , Samet Zihir
IPC: H01Q1/38 , H01Q21/00 , H04B1/44 , H03F1/56 , H03F3/19 , H03G3/30 , H03F3/24 , H03F1/32 , H03F3/195 , H03F3/45 , H03F3/68 , H04B1/04 , H04B1/18 , H04B1/48 , H03K21/10 , H04B7/06 , H01Q1/52 , H01Q3/28 , H01Q3/36 , H01Q19/30 , H01Q21/06 , H03F1/02 , H01Q1/48 , H01Q1/22 , H03H7/48 , H04B1/401
Abstract: An apparatus includes a package and a beam former circuit. The package may be configured to be mounted on an antenna array at a center of four antenna elements. The beam former circuit may (i) be disposed in the package, (ii) have a plurality of ports, (iii) be configured to generate a plurality of radio-frequency signals in the ports while in a transmit mode and (iv) be configured to receive the radio-frequency signals at the ports while in a receive mode. A plurality of ground bumps may be disposed between the beam former circuit and the package. The ground bumps may be positioned to bracket each port. Each ground bump may be electrically connected to a signal ground to create a radio-frequency shielding between neighboring ports.
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公开(公告)号：US10720985B1
公开(公告)日：2020-07-21
申请号：US16354791
申请日：2019-03-15
Applicant: Integrated Device Technology, Inc.
Inventor： Tumay Kanar , Chih-Hsiang Ko
Abstract: An apparatus comprises a phased array antenna panel, a plurality of amplifier circuits, and a plurality of beamformer circuits. The phased array antenna panel generally comprises a plurality of antenna elements. Each of the amplifier circuits is mounted on the phased array antenna panel adjacent to a respective one of the plurality of antenna elements and each of the amplifier circuits has one or more first ports directly coupled to the respective antenna element. Each of the beamformer circuits is mounted on the phased array antenna panel adjacent to a number of the amplifier circuits. Each of the beamformer circuits has one or more second ports directly coupled to each of the adjacent amplifier circuits. Each of the beamformer circuits is generally configured to exchange a plurality of radio-frequency signals with each of the adjacent amplifier circuits via the second ports.
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