公开(公告)号：US09448829B2

公开(公告)日：2016-09-20

申请号：US13730491

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Paolo Narvaez ,  Ganapati N. Srinivasa ,  Eugene Gorbatov ,  Dheeraj R. Subbareddy ,  Mishali Naik ,  Alon Naveh ,  Abirami Prabhakaran ,  Eliezer Weissmann ,  Paul Brett ,  Scott D. Hahn ,  Andrew J. Herdrich ,  Gaurav Khanna ,  Russell J. Fenger ,  Bryant E. Bigbee ,  Andrew D. Henroid ,  David A. Koufaty

IPC: G06F9/00 ,  G06F9/455 ,  G06F9/50 ,  G06F9/38

CPC classification number: G06F9/45558 ,  G06F9/3885 ,  G06F9/5077 ,  G06F2009/4557

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.

Abstract translation: 描述异构处理器架构。 例如，根据本发明的一个实施例的处理器包括：一组两个或更多个小物理处理器核; 至少一个大型物理处理器核具有相对较高性能的处理能力和相对较小的物理处理器核的相对较高的功率使用; 虚拟到物理（V-P）映射逻辑，以通过相应的一组虚拟核心将两个或更多个小物理处理器核心的集合暴露给软件，并从软件中隐藏至少一个大的物理处理器核心。