公开(公告)号：US11182948B2

公开(公告)日：2021-11-23

申请号：US17127740

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Hugues Labbe ,  Tomer Bar-On ,  Gabor Liktor ,  Andrew T. Lauritzen ,  John G. Gierach

IPC: G06T15/00 ,  G06T15/30 ,  G06T15/40 ,  G06T1/20 ,  G06T1/60

Abstract: Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.

公开(公告)号：US11062506B2

公开(公告)日：2021-07-13

申请号：US16916875

申请日：2020-06-30

Applicant: Intel Corporation

Inventor： Andrew T. Lauritzen ,  Altug Koker ,  Louis Feng ,  Tomasz Janczak ,  David M. Cimini ,  Karthik Vaidyanathan ,  Abhishek Venkatesh ,  Murali Ramadoss ,  Michael Apodaca ,  Prasoonkumar Surti

IPC: G06T15/40 ,  G06T15/80 ,  G06T15/00 ,  G06T17/20 ,  G06T15/06 ,  G06T1/20 ,  G06T15/30

Abstract: An embodiment of a graphics pipeline apparatus may include a vertex shader, a visibility shader communicatively coupled to an output of the vertex shader to construct a hierarchical visibility structure, a tile renderer communicatively coupled to an output of the vertex shader and to the visibility shader to perform a tile-based immediate mode render on the output of the vertex shader based on the hierarchical visibility structure, and a rasterizer communicatively coupled to an output of the tile renderer to rasterize the output of the tile renderer based on the hierarchical visibility structure. Other embodiments are disclosed and claimed.

公开(公告)号：US11049214B2

公开(公告)日：2021-06-29

申请号：US16729767

申请日：2019-12-30

Applicant: Intel Corporation

Inventor： Louis Feng ,  Altug Koker ,  Tomasz Janczak ,  Andrew T. Lauritzen ,  David M. Cimini

IPC: G06T1/20 ,  G06T11/40 ,  G06T1/60 ,  G06F9/50

Abstract: Systems, methods and apparatuses may provide for deferred geometry rasterization technology that includes a decision controller to determine, based on available resources in a graphics processor and a view frustum, a first portion of graphics information to be output to the graphics processor and a storage device communicatively coupled to the decision controller to store a second portion of the graphics information for future use. Additionally, an output handler may output the first portion of the graphics information to the graphics processor and swap out the second portion for unused graphics information on the graphics processor.

公开(公告)号：US10896657B2

公开(公告)日：2021-01-19

申请号：US15488561

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Louis Feng ,  Altug Koker ,  Tomasz Janczak ,  Andrew T. Lauritzen ,  David M. Cimini ,  Nikos Kaburlasos ,  Joydeep Ray ,  John H. Feit ,  Travis T. Schluessler ,  Jacek Kwiatkowski ,  Philip R. Laws ,  Devan Burke ,  Elmoustapha Ould-Ahmed-Vall ,  Abhishek R. Appu

IPC: G09G5/00 ,  G09G5/391 ,  G09G5/38 ,  G06T1/20 ,  G09G5/36

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed.

公开(公告)号：US10706612B2

公开(公告)日：2020-07-07

申请号：US15477015

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Andrew T. Lauritzen ,  Altug Koker ,  Louis Feng ,  Tomasz Janczak ,  David M. Cimini ,  Karthik Vaidyanathan ,  Abhishek Venkatesh ,  Murali Ramadoss ,  Michael Apodaca ,  Prasoonkumar Surti

IPC: G06T15/40 ,  G06T15/80 ,  G06T15/00 ,  G06T17/20 ,  G06T15/06 ,  G06T1/20 ,  G06T15/30

Abstract: An embodiment of a graphics pipeline apparatus may include a vertex shader, a visibility shader communicatively coupled to an output of the vertex shader to construct a hierarchical visibility structure, a tile renderer communicatively coupled to an output of the vertex shader and to the visibility shader to perform a tile-based immediate mode render on the output of the vertex shader based on the hierarchical visibility structure, and a rasterizer communicatively coupled to an output of the tile renderer to rasterize the output of the tile renderer based on the hierarchical visibility structure. Other embodiments are disclosed and claimed.

公开(公告)号：US20190095327A1

公开(公告)日：2019-03-28

申请号：US16114593

申请日：2018-08-28

Applicant: Intel Corporation

Inventor： Altug Koker ,  Louis Feng ,  Tomasz Janczak ,  Andrew T. Lauritzen ,  David M Cimini ,  Abhishek R. Appu

IPC: G06F12/0808 ,  G06F12/0811 ,  G06F9/38 ,  G06F12/0897 ,  G06F12/0831 ,  G06T1/20 ,  G06F12/0891 ,  G06F12/0815

Abstract: Systems, apparatuses and methods may provide for technology that detects, by a current stage of a hardware pipeline, a flush request with respect to a first resource and executes, by the current stage, one or more transactions associated with a second resource. Additionally, the current stage may conduct one or more flush operations with respect to the first resource, wherein the one or more transactions associated with the second resource are executed after detection of the flush request and before the one or more flush operations.

公开(公告)号：US20180286112A1

公开(公告)日：2018-10-04

申请号：US15477015

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Andrew T. Lauritzen ,  Altug Koker ,  Louis Feng ,  Tomasz Janczak ,  David M. Cimini ,  Karthik Vaidyanathan ,  Abhishek Venkatesh ,  Murali Ramadoss ,  Michael Apodaca ,  Prasoonkumar Surti

IPC: G06T15/40 ,  G06T15/80 ,  G06T15/00 ,  G06T17/20 ,  G06T15/06 ,  G06T1/20

CPC classification number: G06T15/405 ,  G06T1/20 ,  G06T15/005 ,  G06T15/06 ,  G06T15/30 ,  G06T15/80 ,  G06T17/20

Abstract: An embodiment of a graphics pipeline apparatus may include a vertex shader, a visibility shader communicatively coupled to an output of the vertex shader to construct a hierarchical visibility structure, a tile renderer communicatively coupled to an output of the vertex shader and to the visibility shader to perform a tile-based immediate mode render on the output of the vertex shader based on the hierarchical visibility structure, and a rasterizer communicatively coupled to an output of the tile renderer to rasterize the output of the tile renderer based on the hierarchical visibility structure. Other embodiments are disclosed and claimed.

公开(公告)号：US20180285266A1

公开(公告)日：2018-10-04

申请号：US15477011

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Altug Koker ,  Louis Feng ,  Tomasz Janczak ,  Andrew T. Lauritzen ,  David M Cimini ,  Abhishek R. Appu

IPC: G06F12/0808 ,  G06F9/38 ,  G06T1/20 ,  G06F12/0815 ,  G06F12/0891 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0897

Abstract: Systems, apparatuses and methods may provide for technology that detects, by a current stage of a hardware pipeline, a flush request with respect to a first resource and executes, by the current stage, one or more transactions associated with a second resource. Additionally, the current stage may conduct one or more flush operations with respect to the first resource, wherein the one or more transactions associated with the second resource are executed after detection of the flush request and before the one or more flush operations.

公开(公告)号：US10089230B1

公开(公告)日：2018-10-02

申请号：US15477011

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Altug Koker ,  Louis Feng ,  Tomasz Janczak ,  Andrew T. Lauritzen ,  David M Cimini ,  Abhishek R. Appu

IPC: G06F12/08 ,  G06F12/0808 ,  G06F9/38 ,  G06T1/20 ,  G06F12/0815 ,  G06F12/0891 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0897

Abstract: Systems, apparatuses and methods may provide for technology that detects, by a current stage of a hardware pipeline, a flush request with respect to a first resource and executes, by the current stage, one or more transactions associated with a second resource. Additionally, the current stage may conduct one or more flush operations with respect to the first resource, wherein the one or more transactions associated with the second resource are executed after detection of the flush request and before the one or more flush operations.

公开(公告)号：US20230215400A1

公开(公告)日：2023-07-06

申请号：US18179067

申请日：2023-03-06

Applicant: Intel Corporation

Inventor： Louis Feng ,  Altug Koker ,  Tomasz Janczak ,  Andrew T. Lauritzen ,  David M. Cimini ,  Nikos Kaburlasos ,  Joydeep Ray ,  John H. Feit ,  Travis T. Schluessler ,  Jacek Kwiatkowski ,  Philip R. Laws ,  Devan Burke ,  Elmoustapha Ould-Ahmed-Vall ,  Abhishek R. Appu

IPC: G09G5/00 ,  G09G5/391 ,  G09G5/38 ,  G06T1/20 ,  G09G5/36

CPC classification number: G09G5/005 ,  G06T1/20 ,  G09G5/001 ,  G09G5/38 ,  G09G5/363 ,  G09G5/391 ,  G09G2360/06 ,  G09G2360/08 ,  G09G2360/121 ,  G09G2360/125

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed.