公开(公告)号：US20210065779A1

公开(公告)日：2021-03-04

申请号：US17018071

申请日：2020-09-11

Applicant: Intel Corporation

Inventor： Bhushan M. Borole ,  Iqbal R. Rajwani ,  Anupama A. Thaploo ,  Sunil Nekkanti ,  Altug Koker ,  Abhishek R. Appu

IPC: G11C11/4094 ,  G06F13/40 ,  G06F9/38 ,  G06F9/30 ,  G06F12/0897 ,  G06F12/0868 ,  G06F12/109 ,  G06F12/1027 ,  G06F3/06 ,  G11C11/4074 ,  G11C11/4093 ,  G06F12/08

Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.

公开(公告)号：US10790010B2

公开(公告)日：2020-09-29

申请号：US16435878

申请日：2019-06-10

Applicant: Intel Corporation

Inventor： Bhushan M. Borole ,  Iqbal R. Rajwani ,  Anupama A. Thaploo ,  Sunil Nekkanti ,  Altug Koker ,  Abhisek R. Appu

IPC: G11C7/00 ,  G11C11/4094 ,  G06F13/40 ,  G06F9/38 ,  G06F9/30 ,  G06F12/0897 ,  G06F12/0868 ,  G06F12/109 ,  G06F12/1027 ,  G06F3/06 ,  G11C11/4074 ,  G11C11/4093 ,  G06F12/08 ,  G11C11/419

Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.

公开(公告)号：US20200160819A1

公开(公告)日：2020-05-21

申请号：US16658793

申请日：2019-10-21

Applicant: Intel Corporation

Inventor： Sanjeev S. Jahagirdar ,  Tapan A. Ganpule ,  Anupama A. Thaploo ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker

IPC: G09G5/393 ,  G09G5/399 ,  G06F13/40 ,  G09G5/02 ,  G09G5/37 ,  G09G5/34 ,  H03K19/00 ,  H03K19/08 ,  G06F3/14 ,  G09G5/36

Abstract: Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200019207A1

公开(公告)日：2020-01-16

申请号：US16527165

申请日：2019-07-31

Applicant: Intel Corporation

Inventor： Iqbal R. Rajwani ,  Altug Koker ,  Bhushan M. Borole ,  Kamal Sinha ,  Abhishek R. Appu ,  Anupama A. Thaploo ,  Sunil Nekkanti ,  Wenyin Fu

IPC: G06F1/06 ,  G06F9/30 ,  G06F9/38 ,  G06F13/16 ,  G06F1/08 ,  H03K19/096 ,  G06T1/60

Abstract: In an embodiment, a processor includes at least one processor core and at least one graphics processor. The at least one graphics processor may include a register file having a plurality of entries, where at least a portion of the at least one graphics processor is to operate at a first operating frequency and the register file is to operate at a second operating frequency greater than the first operating frequency, to enable the at least one graphics processor to issue a plurality of write requests to the register file in a single clock cycle at the first operating frequency and receive a plurality of data elements of a plurality of read requests from the register file in the single clock cycle at the first operating frequency. Other embodiments are described and claimed.

公开(公告)号：US10410699B1

公开(公告)日：2019-09-10

申请号：US16024441

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Anupama A. Thaploo ,  Bhushan Borole ,  Muhammad M. Khellah ,  Pascal A. Meinerzhagen

IPC: G11C7/22 ,  G01R31/3185

Abstract: Some embodiments include apparatuses having a plurality of latches, each of the latches including a first input node to receive first information during a first mode of the apparatus, a second input node to receive second information during a second mode of the apparatus, a first clock node to receive a first signal, a second clock node to receive a second signal, a third clock node to receive a third signal, and a fourth clock node to receive a fourth signal; a first conductive connection coupled between an output node of a first latch among the latches and the first input node of a second latch among the latches; a second conductive connection coupled between an output node of the second latch and the first input node of a third latch among the latches; and a third conductive connection coupled between an output node of the third latch and the first input node of a fourth latch among the latches.

公开(公告)号：US20190266981A1

公开(公告)日：2019-08-29

申请号：US16400919

申请日：2019-05-01

Applicant: Intel Corporation

Inventor： Sanjeev S. Jahagirdar ,  Tapan A. Ganpule ,  Anupama A. Thaploo ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker

IPC: G09G5/393 ,  G09G5/399 ,  G06F3/14 ,  G09G5/36 ,  G09G5/02 ,  H03K19/00 ,  G09G5/34 ,  G06F13/40 ,  H03K19/08 ,  G09G5/37

Abstract: Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.

公开(公告)号：US10347324B2

公开(公告)日：2019-07-09

申请号：US16054207

申请日：2018-08-03

Applicant: Intel Corporation

Inventor： Bhushan M. Borole ,  Iqbal R. Rajwani ,  Anupama A. Thaploo ,  Sunil Nekkanti ,  Altug Koker ,  Abhisek R. Appu

IPC: G11C7/00 ,  G11C11/4094 ,  G06F13/40 ,  G06F9/38 ,  G06F12/08 ,  G06F9/30 ,  G06F3/06 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/419

Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.

公开(公告)号：US20180302064A1

公开(公告)日：2018-10-18

申请号：US15488628

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Bhushan M. Borole ,  Anupama A. Thaploo ,  Altug Koker ,  Abhishek R. Appu ,  Kamal Sinha ,  Wenyin Fu

IPC: H03K3/012 ,  H03K3/356 ,  H03K19/21

CPC classification number: H03K3/012 ,  H03K3/35606 ,  H03K19/215

Abstract: A pulse triggered flip flop circuit includes an exclusive OR clock generating stage that receives an input clock, data and produces an output clock pulse. The stage produces a output clock pulse that only goes away when the data is fully captured. The stage disables the output clock pulse only when the data is fully captured. Moreover, the circuit only toggles when the input data changes, reducing power consumption in some embodiments.

公开(公告)号：US20180300137A1

公开(公告)日：2018-10-18

申请号：US15488947

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Anupama A. Thaploo ,  Bhushan M. Borole ,  Bee Ngo ,  Iqbal R. Rajwani ,  Altug Koker ,  Abhishek R. Appu ,  Kamal Sinha ,  Wenyin Fu

IPC: G06F9/30 ,  G11C17/18 ,  G11C17/16 ,  G06F13/40

CPC classification number: G06F9/30105 ,  G06F13/4068 ,  G06F13/4077 ,  G11C7/12 ,  G11C11/4094 ,  G11C17/16 ,  G11C17/18

Abstract: By shutting off keeper transistors during pre-charge, the aging on these devices may be reduced. This means that a relatively weaker keeper may be used for noise compared to an overdesigned stronger keeper. Using a relatively weaker keeper circuit results in a faster evaluation stage and improved minimum read voltage in some embodiments.