公开(公告)号：US10324721B2

公开(公告)日：2019-06-18

申请号：US15488947

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Anupama A. Thaploo ,  Bhushan M. Borole ,  Bee Ngo ,  Iqbal R. Rajwani ,  Altug Koker ,  Abhishek R. Appu ,  Kamal Sinha ,  Wenyin Fu

IPC: G11C11/00 ,  G06F9/30 ,  G11C17/18 ,  G11C17/16 ,  G06F13/40 ,  G11C11/4094 ,  G11C7/12

Abstract: By shutting off keeper transistors during pre-charge, the aging on these devices may be reduced. This means that a relatively weaker keeper may be used for noise compared to an overdesigned stronger keeper. Using a relatively weaker keeper circuit results in a faster evaluation stage and improved minimum read voltage in some embodiments.

公开(公告)号：US20180300137A1

公开(公告)日：2018-10-18

申请号：US15488947

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Anupama A. Thaploo ,  Bhushan M. Borole ,  Bee Ngo ,  Iqbal R. Rajwani ,  Altug Koker ,  Abhishek R. Appu ,  Kamal Sinha ,  Wenyin Fu

IPC: G06F9/30 ,  G11C17/18 ,  G11C17/16 ,  G06F13/40

CPC classification number: G06F9/30105 ,  G06F13/4068 ,  G06F13/4077 ,  G11C7/12 ,  G11C11/4094 ,  G11C17/16 ,  G11C17/18

Abstract: By shutting off keeper transistors during pre-charge, the aging on these devices may be reduced. This means that a relatively weaker keeper may be used for noise compared to an overdesigned stronger keeper. Using a relatively weaker keeper circuit results in a faster evaluation stage and improved minimum read voltage in some embodiments.

公开(公告)号：US10754809B2

公开(公告)日：2020-08-25

申请号：US16354312

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Anupama A. Thaploo ,  Bhushan M. Borole ,  Bee Ngo ,  Iqbal R. Rajwani ,  Altug Koker ,  Abhishek R. Appu ,  Kamal Sinha ,  Wenyin Fu

IPC: G06F13/40 ,  G11C17/18 ,  G11C17/16 ,  G11C11/4094 ,  G06F9/30 ,  G11C7/12

Abstract: By shutting off keeper transistors during pre-charge, the aging on these devices may be reduced. This means that a relatively weaker keeper may be used for noise compared to an overdesigned stronger keeper. Using a relatively weaker keeper circuit results in a faster evaluation stage and improved minimum read voltage in some embodiments.

公开(公告)号：US20190213161A1

公开(公告)日：2019-07-11

申请号：US16354312

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Anupama A. Thaploo ,  Bhushan M. Borole ,  Bee Ngo ,  Iqbal R. Rajwani ,  Altug Koker ,  Abhishek R. Appu ,  Kamal Sinha ,  Wenyin Fu

IPC: G06F13/40 ,  G06F9/30 ,  G11C17/18 ,  G11C11/4094 ,  G11C17/16

CPC classification number: G06F13/4068 ,  G06F9/30105 ,  G06F9/30141 ,  G06F13/4077 ,  G11C7/12 ,  G11C11/4094 ,  G11C17/16 ,  G11C17/18

Abstract: By shutting off keeper transistors during pre-charge, the aging on these devices may be reduced. This means that a relatively weaker keeper may be used for noise compared to an overdesigned stronger keeper. Using a relatively weaker keeper circuit results in a faster evaluation stage and improved minimum read voltage in some embodiments.