公开(公告)号：US20190228160A1

公开(公告)日：2019-07-25

申请号：US16370566

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Mikal Hunsaker ,  Mark Feuerstraeter ,  Asad Azam ,  Zhenyu Zhu ,  Navtej Singh

IPC: G06F21/57 ,  G05B9/02 ,  G05B19/042

Abstract: Methods, systems and apparatuses may provide for technology that includes a system on chip (SoC) having a root of trust and an embedded controller to conduct functional safety operations and non-functional safety operations with respect to the SoC. The technology may also include an enhanced serial peripheral interface (eSPI) coupled to the SoC and the embedded controller, wherein the eSPI is to tunnel communications associated with the functional safety operations between the embedded controller and the root of trust.

公开(公告)号：US20190227121A1

公开(公告)日：2019-07-25

申请号：US16370993

申请日：2019-03-30

Applicant: Intel Corporation

Inventor： Asad Azam ,  R Selvakumar Raja Gopal ,  Kaitlyn Chen

IPC: G01R31/3187 ,  G06F11/10 ,  G06F11/07

Abstract: Technologies for built-in self-testing of a memory array using error detection and correction code knowledge include identifying data errors between pseudo random data written to the memory array and the data read back from the memory array and ignoring those data errors determined to be correctable. The data errors may be determined to be correctable if an error corrector circuit can correct those errors or if the number of errors per memory chuck is less than a number of errors correctable by the error correct circuit.

公开(公告)号：US12073225B2

公开(公告)日：2024-08-27

申请号：US17097055

申请日：2020-11-13

Applicant: Intel Corporation

Inventor： Subrata Banik ,  Asad Azam ,  Vincent James Zimmer ,  Rajaram Regupathy

IPC: G06F9/4401 ,  G06F3/06 ,  G06F13/16

CPC classification number: G06F9/4403 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/068 ,  G06F13/1668

Abstract: A data processing system comprises a processing core to execute a basic input/output system (BIOS) as part of a boot process. The data processing system also comprises static random-access memory (SRAM) in communication with the processing core. The data processing system also comprises a pre-BIOS component in communication with the SRAM. The pre-BIOS component is configured to execute a pre-BIOS block before the processing core begins executing the BIOS. The pre-BIOS block, when executed by the pre-BIOS component, causes the pre-BIOS component to (a) initialize the pre-BIOS component, (b) measure an amount of time taken to initialize the pre-BIOS component, and (c) save the measured amount of time to the SRAM as a pre-BIOS boot-time record. Other embodiments are described and claimed.

公开(公告)号：US11941409B2

公开(公告)日：2024-03-26

申请号：US16914331

申请日：2020-06-27

Applicant: Intel Corporation

Inventor： Subrata Banik ,  Asad Azam ,  Jenny M. Pelner ,  Vincent Zimmer ,  Rajaram Regupathy

IPC: G06F9/44 ,  G06F9/4401

CPC classification number: G06F9/4403 ,  G06F2212/60

Abstract: Systems, methods, and apparatuses relating to circuitry to implement a multiprocessor boot flow for a faster boot process are described. In one embodiment, a system includes a hardware processor comprising a processor core, a cache coupled to the hardware processor, storage for hardware initialization code, and a controller circuit to initialize a portion of the cache as memory for usage by the hardware initialization code before beginning execution of the hardware initialization code after a power on of the system.

公开(公告)号：US11841776B2

公开(公告)日：2023-12-12

申请号：US16439407

申请日：2019-06-12

Applicant: Intel Corporation

Inventor： Nabajit Deka ,  Riccardo Mariani ,  Asad Azam ,  Roger May ,  Prashanth Gadila

IPC: G06F11/00 ,  G06F11/16 ,  G05B9/02 ,  G06F11/30 ,  G06F13/12 ,  G06F11/07

CPC classification number: G06F11/1641 ,  G05B9/02 ,  G06F11/0796 ,  G06F11/3055 ,  G06F13/122

Abstract: Methods, systems and apparatuses may provide for technology that includes a chip having a first die including a first processing logic to execute a first application instance and generate a first output of the first application instance, and a second processing logic to execute a second application instance and generate a second output of the second application instance. The chip may also include a second die coupled to the first die, wherein the second die includes a safety monitor detect a condition associated with one or more of an error in the first output, an error in the second output, or a discrepancy between the first output and the second output. The safety monitor may also initiate a transition of the chip into a safe state in response to the condition.

公开(公告)号：US11335428B2

公开(公告)日：2022-05-17

申请号：US16155606

申请日：2018-10-09

Applicant: Intel Corporation

Inventor： Asad Azam ,  R Selvakumar Raja Gopal ,  Sreejit Chakravarty ,  Kaitlyn Chen

IPC: G11C29/42 ,  G11C29/36 ,  G11C29/04 ,  G01R31/3177 ,  G06F11/16 ,  G01R31/317 ,  G01R31/3183 ,  G01R31/3181 ,  G06F11/263 ,  G06F30/333 ,  G01R31/3185

Abstract: The disclosed embodiments relate to method, apparatus and system for testing memory circuitry and diagnostic components designed to test the memory circuitry. The memory may be tested regularly using Memory Built-In Self-Test (MBIST) to detect memory failure. Error Correction Code (ECC)/Parity is implemented for SRAM/Register Files/ROM memory structures to protect against transient and permanent faults during runtime. ECC/Parity encoder and decoder logic detect failure on both data and address buses and are intended to catch soft error or structural fault in address decoding logic in SRAM Controller, where data may be read/written from/to different locations due to faults. ECC/parity logic on the memory structures are subject to failures. In certain exemplary embodiments, an array test controller is used to generate and transmit error vectors to thereby determine faulty diagnostic components. The test vectors may be generated randomly to test the diagnostic components during run-time for in-field testing.

公开(公告)号：US11243585B2

公开(公告)日：2022-02-08

申请号：US16795919

申请日：2020-02-20

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Rao Jagannadha Rapeta ,  Asad Azam

IPC: G05D23/19 ,  G06F1/20 ,  G05B15/02

Abstract: The disclosed embodiments relate to methods, systems and apparatus for dynamic temperature aware functional safety. The disclosed embodiments provide adaptive techniques to track extended dynamic temperature range of a System-on-Chip (SOC) and automatically tune critical IP components of the SOC so that system can operate reliably even at high temperatures. The disclosed embodiments relax the overdesign of the SOC components by reusing existing components such as a ring oscillator to determine temperature at different regions of the SOC. In one embodiment, the disclosed principles use a Calibrated Ring Oscillator (CRO) temperature sensors. The CRO-based temperature sensors provide fast temperature measurement suitable for detecting dynamic temperature ranges and temperature rate of change. The CROs are existing on the SOC and do not require addition of additional sensors.

公开(公告)号：US11120642B2

公开(公告)日：2021-09-14

申请号：US16019945

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Jagannadha Rao Rapeta ,  Asad Azam ,  Amit Kumar Srivastava

IPC: G07C5/00 ,  H04R1/32 ,  H04R29/00 ,  G08B29/12 ,  G07C5/08

Abstract: Methods and apparatus relating to functional safety critical audio system for autonomous and industrial applications are described. In an embodiment, safety island logic circuitry transmits an enable signal to cause initiation of a functional safety test for an audio component in a vehicle. Audio processing logic circuitry receives the enable signal and causes activation of power amplifier logic circuitry, in response to the enable signal, to drive the audio component in accordance with an audio alert test signal. The audio component includes a Parametric Acoustic Array (PAA) transducer. Other embodiments are also disclosed and claimed.

公开(公告)号：US10955805B2

公开(公告)日：2021-03-23

申请号：US16155495

申请日：2018-10-09

Applicant: Intel Corporation

Inventor： Nabajit Deka ,  Riccardo Mariani ,  Asad Azam ,  Rajesh Banginwar ,  Wenjun Zhang

IPC: G06F11/00 ,  G05B19/042 ,  G06F11/07

Abstract: An apparatus of a System on Chip (SoC) to implement a one out of two diagnostics (1oo2D) safety system comprises a memory comprising firmware to provide monitoring of the SoC and a second SoC, and a communication interface to provide cross-monitoring between the SoC and the second SoC. The firmware and the communication interface enable the SoC and the second SoC to implement the 1oo2D safety system without significant hardware or software external to the SoC.

公开(公告)号：US10664027B2

公开(公告)日：2020-05-26

申请号：US16155749

申请日：2018-10-09

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Rao Jagannadha Rapeta ,  Asad Azam

IPC: G05D23/00 ,  G06F1/20 ,  G05B15/02

Abstract: The disclosed embodiments relate to methods, systems and apparatus for dynamic temperature aware functional safety. The disclosed embodiments provide adaptive techniques to track extended dynamic temperature range of a System-on-Chip (SOC) and automatically tune critical IP components of the SOC so that system can operate reliably even at high temperatures. The disclosed embodiments relax the overdesign of the SOC components by reusing existing components such as a ring oscillator to determine temperature at different regions of the SOC. In one embodiment, the disclosed principles use a Calibrated Ring Oscillator (CRO) temperature sensors. The CRO-based temperature sensors provide fast temperature measurement suitable for detecting dynamic temperature ranges and temperature rate of change. The CROs are existing on the SOC and do not require addition of additional sensors.