公开(公告)号：US11086812B2

公开(公告)日：2021-08-10

申请号：US14998222

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Mikal C. Hunsaker ,  Shaun M. Conrad ,  Zhenyu Zhu ,  Navtej Singh

IPC: G06F13/42 ,  G06F13/362 ,  G06F13/40

Abstract: An embedded controller is provided for a computer, including a processor, first one or more logic elements providing a serial peripheral interface (SPI) module to communicatively couple the embedded controller to an SPI bus as an SPI slave, and second one or more logic elements providing a platform environment control interface (PECI)-over-SPI engine, to build an SPI packet providing an encapsulated PECI command and send a notification to an SPI master that the packet is available.

公开(公告)号：US11113402B2

公开(公告)日：2021-09-07

申请号：US16370566

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Mikal Hunsaker ,  Mark Feuerstraeter ,  Asad Azam ,  Zhenyu Zhu ,  Navtej Singh

IPC: G06F9/00 ,  G06F15/177 ,  G06F21/57 ,  G05B9/02 ,  G05B19/042

Abstract: Methods, systems and apparatuses may provide for technology that includes a system on chip (SoC) having a root of trust and an embedded controller to conduct functional safety operations and non-functional safety operations with respect to the SoC. The technology may also include an enhanced serial peripheral interface (eSPI) coupled to the SoC and the embedded controller, wherein the eSPI is to tunnel communications associated with the functional safety operations between the embedded controller and the root of trust.

公开(公告)号：US20170185559A1

公开(公告)日：2017-06-29

申请号：US14998222

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Mikal C. Hunsaker ,  Shaun M. Conrad ,  Zhenyu Zhu ,  Navtej Singh

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/362

CPC classification number: G06F13/4282 ,  G06F13/362 ,  G06F13/4068

Abstract: An embedded controller is provided for a computer, including a processor, first one or more logic elements providing a serial peripheral interface (SPI) module to communicatively couple the embedded controller to an SPI bus as an SPI slave, and second one or more logic elements providing a platform environment control interface (PECI)-over-SPI engine, to build an SPI packet providing an encapsulated PECI command and send a notification to an SPI master that the packet is available.

公开(公告)号：US20190228160A1

公开(公告)日：2019-07-25

申请号：US16370566

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Mikal Hunsaker ,  Mark Feuerstraeter ,  Asad Azam ,  Zhenyu Zhu ,  Navtej Singh

IPC: G06F21/57 ,  G05B9/02 ,  G05B19/042

Abstract: Methods, systems and apparatuses may provide for technology that includes a system on chip (SoC) having a root of trust and an embedded controller to conduct functional safety operations and non-functional safety operations with respect to the SoC. The technology may also include an enhanced serial peripheral interface (eSPI) coupled to the SoC and the embedded controller, wherein the eSPI is to tunnel communications associated with the functional safety operations between the embedded controller and the root of trust.