公开(公告)号：US11579880B2

公开(公告)日：2023-02-14

申请号：US17240882

申请日：2021-04-26

Applicant: INTEL CORPORATION

Inventor： Bret Toll ,  Christopher J. Hughes ,  Dan Baum ,  Elmoustapha Ould-Ahmed-Vall ,  Raanan Sade ,  Robert Valentine ,  Mark J. Charney ,  Alexander F. Heinecke

IPC: G06F9/30

Abstract: Disclosed embodiments relate to systems for performing instructions to quickly convert and use matrices (tiles) as one-dimensional vectors. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode, locations of a two-dimensional (2D) matrix and a one-dimensional (1D) vector, and a group of elements comprising one of a row, part of a row, multiple rows, a column, part of a column, multiple columns, and a rectangular sub-tile of the specified 2D matrix, and wherein the opcode is to indicate a move of the specified group between the 2D matrix and the 1D vector, decode circuitry to decode the fetched instruction; and execution circuitry, responsive to the decoded instruction, when the opcode specifies a move from 1D, to move contents of the specified 1D vector to the specified group of elements.

公开(公告)号：US11507376B2

公开(公告)日：2022-11-22

申请号：US17152160

申请日：2021-01-19

Applicant: INTEL CORPORATION

Inventor： Bret Toll ,  Alexander F. Heinecke ,  Christopher J. Hughes ,  Ronen Zohar ,  Michael Espig ,  Dan Baum ,  Raanan Sade ,  Robert Valentine ,  Mark J. Charney ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06F17/16 ,  G06F12/02 ,  G06F9/30 ,  G06F12/06 ,  G06F9/38 ,  G06T1/20 ,  G06F3/06 ,  G06F12/0897 ,  G06F12/0875 ,  G06F9/345

Abstract: Disclosed embodiments relate to instructions for fast element unpacking. In one example, a processor includes fetch circuitry to fetch an instruction whose format includes fields to specify an opcode and locations of an Array-of-Structures (AOS) source matrix and one or more Structure of Arrays (SOA) destination matrices, wherein: the specified opcode calls for unpacking elements of the specified AOS source matrix into the specified Structure of Arrays (SOA) destination matrices, the AOS source matrix is to contain N structures each containing K elements of different types, with same-typed elements in consecutive structures separated by a stride, the SOA destination matrices together contain K segregated groups, each containing N same-typed elements, decode circuitry to decode the fetched instruction, and execution circuitry, responsive to the decoded instruction, to unpack each element of the specified AOS matrix into one of the K element types of the one or more SOA matrices.

公开(公告)号：US11294671B2

公开(公告)日：2022-04-05

申请号：US16232931

申请日：2018-12-26

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Michael Espig ,  Dan Baum ,  Robert Valentine ,  Bret Toll ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06F9/30 ,  G06F17/16

Abstract: Disclosed embodiments relate to systems and methods for performing duplicate detection instructions on two-dimensional (2D) data. In one example, a processor includes fetch circuitry to fetch an instruction, decode circuitry to decode the fetched instruction having fields to specify an opcode and locations of a source matrix comprising M×N elements and a destination, the opcode to indicate execution circuitry is to use a plurality of comparators to discover duplicates in the source matrix, and store indications of locations of discovered duplicates in the destination. The execution circuitry to execute the decoded instruction as per the opcode.

公开(公告)号：US10990396B2

公开(公告)日：2021-04-27

申请号：US16145066

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Bret Toll ,  Christopher J. Hughes ,  Dan Baum ,  Elmoustapha Ould-Ahmed-Vall ,  Raanan Sade ,  Robert Valentine ,  Mark J. Charney ,  Alexander F. Heinecke

IPC: G06F9/30

Abstract: Disclosed embodiments relate to systems for performing instructions to quickly convert and use matrices (tiles) as one-dimensional vectors. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode, locations of a two-dimensional (2D) matrix and a one-dimensional (1D) vector, and a group of elements comprising one of a row, part of a row, multiple rows, a column, part of a column, multiple columns, and a rectangular sub-tile of the specified 2D matrix, and wherein the opcode is to indicate a move of the specified group between the 2D matrix and the 1D vector, decode circuitry to decode the fetched instruction; and execution circuitry, responsive to the decoded instruction, when the opcode specifies a move from 1D, to move contents of the specified 1D vector to the specified group of elements.

公开(公告)号：US10545757B2

公开(公告)日：2020-01-28

申请号：US13730752

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Matt Walsh ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Bret Toll

IPC: G06F9/30

Abstract: Systems, apparatuses, and methods for performing an instruction in a computer processor are described. For example, an instruction having a source and destination operand is executed to determine whether all data elements of the source operand are equal and an indication of the determination is stored in the destination operand.

公开(公告)号：US20190303167A1

公开(公告)日：2019-10-03

申请号：US15942201

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Christopher J. HUGHES ,  Alexander F. HEINECKE ,  Robert Valentine ,  Bret Toll ,  Jesus Corbal ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06F9/38 ,  G06F9/30

Abstract: Disclosed embodiments relate to systems and methods for implementing chained tile operations. In one example, a processor includes fetch circuitry to fetch one or more instructions until a plurality of instructions has been fetched, each instruction to specify source and destination tile operands, decode circuitry to decode the fetched instructions, and execution circuitry, responsive to the decoded instructions, to: identify first and second decoded instructions belonging to a chain of instructions, dynamically select and configure a SIMD path comprising first and second processing engines (PE) to execute the first and second decoded instructions, and set aside the specified destination of the first decoded instruction, and instead route a result of the first decoded instruction from the first PE to be used by the second PE to perform the second decoded instruction.

公开(公告)号：US20190042541A1

公开(公告)日：2019-02-07

申请号：US15859271

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Raanan Sade ,  Simon Rubanovich ,  Amit Gradstein ,  Zeev Sperber ,  Alexander Heinecke ,  Robert Valentine ,  Mark J. Charney ,  Bret Toll ,  Jesus Corbal ,  Elmoustapha Ould-Ahmed-Vall ,  Menachem Adelman

IPC: G06F17/16 ,  G06F9/30

Abstract: Embodiments detailed herein relate to matrix operations. For example, embodiments of instruction support for matrix (tile) dot product operations are detailed. Exemplary instructions including computing a dot product of signed words and accumulating in a quadword data elements of a matrix pair. Additionally, in some instances, non-accumulating quadword data elements of the matrix pair are set to zero.

公开(公告)号：US10153012B2

公开(公告)日：2018-12-11

申请号：US15855609

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Glenn Hinton ,  Bret Toll ,  Ronak Singhal

IPC: G06F9/30 ,  G11C7/10

Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.

公开(公告)号：US09786338B2

公开(公告)日：2017-10-10

申请号：US15238186

申请日：2016-08-16

Applicant: Intel Corporation

Inventor： Glenn Hinton ,  Bret Toll ,  Ronak Singhal

IPC: G06F9/30 ,  G11C7/10

CPC classification number: G11C7/1036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30163

Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.

公开(公告)号：US20150006848A1

公开(公告)日：2015-01-01

申请号：US13931008

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Glenn Hinton ,  Bret Toll ,  Ronak Singhal

IPC: G06F9/30

CPC classification number: G11C7/1036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30163

Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.

Abstract translation: 处理器包括N位寄存器和用于接收多寄存器存储器访问指令的解码单元。 多寄存器存储器访问指令是指示存储器位置和寄存器。 处理器包括与解码单元和N位寄存器耦合的存储器存取单元。 存储器访问单元响应于多个寄存器存储器访问指令执行多个寄存器存储器存取操作。 该操作涉及在包括指定的寄存器的每个N位寄存器中涉及N位数据。 该操作还涉及对应于所指示的存储器位置的M×N位存储器线的不同对应的N位部分。 要在多个寄存器存储器访问操作中涉及的N位寄存器中的N位数据的总位数至少等于存储器行的M×N位的至少一半。