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    Multinode hubs for trusted computing
    21.
    发明授权
    Multinode hubs for trusted computing 有权
    用于可信计算的多中心

    公开(公告)号：US09413765B2

    公开(公告)日：2016-08-09

    申请号：US14225140

    申请日：2014-03-25

    Applicant: INTEL CORPORATION

    Inventor： Robert C. Swanson ,  Daniel Nemiroff ,  Vincent J. Zimmer ,  Mallik Bulusu ,  John R. Lindsley ,  Robert W. Cone ,  Malay Trivedi ,  Piotr Kwidzinski

    IPC: H04L29/06 ,  G06F21/55 ,  G06F21/57

    CPC classification number: H04L63/10 ,  G06F3/0622 ,  G06F3/0637 ,  G06F3/0683 ,  G06F13/28 ,  G06F21/554 ,  G06F21/57 ,  G06F21/572

    Abstract: Embodiments of multinode hubs for trust operations are disclosed herein. In some embodiments, a multinode hub may include a plurality of memory regions, a trapping module, and a trusted platform module (TPM) component. Each memory region may be associated with and receive trust operation data from a coherent computing node. The trapping module may generate trap notifications in response to accesses to the plurality of memory regions by the associated coherent computing nodes. The trap notifications may indicate which of the plurality of memory locations has been accessed, and the TPM component may process the trust operation data in a memory region indicated by a trap notification. Other embodiments may be disclosed and/or claimed.

    Abstract translation: 本文公开了用于信任操作的多节点集线器的实施例。 在一些实施例中，多节点集线器可以包括多个存储器区域，陷阱模块和可信平台模块（TPM）组件。 每个存储器区域可以与相干计算节点相关联并接收来自相干计算节点的信任操作数据。 捕获模块可以响应于相关联的相干计算节点对多个存储器区域的访问而产生陷阱通知。 陷阱通知可以指示已经访问了多个存储器位置中的哪一个，并且TPM组件可以处理由陷阱通知指示的存储器区域中的信任操作数据。 可以公开和/或要求保护其他实施例。

    Public key infrastructure for system-on-chip
    22.
    发明授权
    Public key infrastructure for system-on-chip 有权
    公共密钥基础设施系统级芯片

    公开(公告)号：US09319224B2

    公开(公告)日：2016-04-19

    申请号：US14039667

    申请日：2013-09-27

    Applicant: INTEL CORPORATION

    Inventor： Daniel Nemiroff ,  William Stevens, Jr.

    IPC: H04L29/06 ,  H04L9/32 ,  G09C1/00

    CPC classification number: H04L9/3263 ,  G09C1/00

    Abstract: The present disclosure is generally related to embedding public key infrastructure information to a system-on-chip (SOC). The method includes generating a key pair including a public key and a private key. The method includes creating a digital certificate corresponding to the public key. The method includes signing the digital certificate with a unique signature. The method includes extracting the public key and the unique signature into a key file, wherein the key file is to be stored in a plurality of silicon fuses on the SOC.

    Abstract translation: 本公开通常涉及将公共密钥基础设施信息嵌入到片上系统（SOC）。 该方法包括生成包括公钥和私钥的密钥对。 该方法包括创建对应于公钥的数字证书。 该方法包括使用唯一签名签署数字证书。 该方法包括将公钥和唯一签名提取到密钥文件中，其中密钥文件将存储在SOC上的多个硅熔丝中。

    CRYPTOGRAPHIC KEY GENERATION USING A STORED INPUT VALUE AND A STORED COUNT VALUE
    23.
    发明申请
    CRYPTOGRAPHIC KEY GENERATION USING A STORED INPUT VALUE AND A STORED COUNT VALUE 审中-公开
    使用存储的输入值和存储的计数值进行CRYPTOGRAPHIC KEY GENERATION

    公开(公告)号：US20150188705A1

    公开(公告)日：2015-07-02

    申请号：US14636717

    申请日：2015-03-03

    Applicant: Intel Corporation

    Inventor： Daniel Nemiroff

    IPC: H04L9/08 ,  H04L9/32

    CPC classification number: H04L9/0869 ,  G06F7/582 ,  G06F7/588 ,  H04L9/0662 ,  H04L9/0861 ,  H04L9/3249 ,  H04L2209/24 ,  H04L2209/72

    Abstract: Embodiments of an invention for cryptographic key generation using a stored input value and a stored count value have been described. In one embodiment, a processor includes non-volatile storage storing an input value and a count value, and logic to generate a cryptographic key based on the stored input value and the stored count value.

    Abstract translation: 已经描述了使用存储的输入值和存储的计数值的密码密钥生成的发明的实施例。 在一个实施例中，处理器包括存储输入值和计数值的非易失性存储器，以及基于存储的输入值和存储的计数值来产生密码密钥的逻辑。

    DETECTING LASER-INJECTED FAULTS
    24.
    发明公开
    DETECTING LASER-INJECTED FAULTS 审中-公开

    公开(公告)号：US20240005962A1

    公开(公告)日：2024-01-04

    申请号：US17856897

    申请日：2022-07-01

    Applicant: Intel Corporation

    Inventor： Minki Cho ,  Daniel Nemiroff ,  Carlos Tokunaga ,  James W. Tschanz ,  Kah Meng Yeem ,  Yaxin Shui

    IPC: G11C5/00

    CPC classification number: G11C5/005

    Abstract: An integrated circuit (IC) die comprises a sensor, which includes a pulse generator and a pulse expander. The pulse generator comprises gate circuits coupled to each other in an in-series arrangement. An input of the pulse generator is coupled to receive a voltage and the pulse generator is to generate a first signal based on the voltage. The pulse generator is to generate a first pulse of the first signal based on an event wherein radiation from a laser is incident upon the pulse generator. The pulse expander is coupled to receive the first signal from the pulse generator and to generate a second signal based on the first signal, wherein a second pulse of the second signal is based on the first pulse. A first duration of the first pulse is less than a second duration of the second pulse.

    ENCODING PROCESS FOR MULTIPLE RSA AND ECC KEYS
    29.
    发明申请
    ENCODING PROCESS FOR MULTIPLE RSA AND ECC KEYS 审中-公开

    公开(公告)号：US20190044716A1

    公开(公告)日：2019-02-07

    申请号：US16142587

    申请日：2018-09-26

    Applicant: Intel Corporation

    Inventor： Daniel Nemiroff ,  Xiaoyu Ruan ,  William Stevens, JR.

    IPC: H04L9/08 ,  H04L9/30 ,  H04L9/32 ,  H04L9/14

    Abstract: In embodiments, an apparatus for microcontroller (μC) or system-on-chip (SoC) computing includes a set of fuses disposed in a μC or a SoC to store a seed value and M pairs of loop counter values (LCVs) with which to locally generate M private keys from the seed value on the microcontroller or SoC, where M is a positive integer, each private key to decrypt data encrypted with a pre-defined public key cryptosystem, wherein each private key includes two prime numbers p and q (p,q), the LCVs being a number of iterations of a key derivation function (KDF) needed to respectively obtain p and q from the seed value; and a key decoder, disposed in the (μC) or the SoC, and coupled to the set of fuses, to read the seed value and the M pairs of LCVs, and, for each of the M private keys to: respectively generate (p,q) from the seed value by respectively iterating the KDF by the LCVs for that key.

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