公开(公告)号：US12265440B2

公开(公告)日：2025-04-01

申请号：US18455008

申请日：2023-08-24

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

IPC: G06F1/00 ,  G06F1/324 ,  G06F1/3296

Abstract: A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.

公开(公告)号：US11762449B2

公开(公告)日：2023-09-19

申请号：US17563605

申请日：2021-12-28

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Efraim Rotem ,  Nir Rosenzweig ,  Krishnakanth V. Sistla ,  Ashish V. Choubal ,  Ankush Varma

IPC: G06F1/32 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3237

CPC classification number: G06F1/324 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/3203 ,  G06F1/3237 ,  Y02D10/00

Abstract: Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.

公开(公告)号：US11740682B2

公开(公告)日：2023-08-29

申请号：US17824984

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

IPC: G06F1/00 ,  G06F1/324 ,  G06F1/3296

CPC classification number: G06F1/324 ,  G06F1/3296

Abstract: A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.

公开(公告)号：US11703927B2

公开(公告)日：2023-07-18

申请号：US16833328

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Oren Zonensain ,  Roman Rechter ,  Almog Reshef ,  Maxim Levit ,  Nadav Shulman ,  Efraim Rotem

IPC: G06F1/00 ,  G06F11/30 ,  G06F1/28 ,  G01R31/52

CPC classification number: G06F1/28 ,  G01R31/52

Abstract: A performance management scheme for a processor based on leakage current measurement in field. The scheme performs the operations of detection and correction. The operation of detection measures per core leakage current in the field (e.g., using voltage regulator electrical current counters). The operation of correction changes the processor power management behavior. For example, processor cores showing high leakage degradation may be logically swapped with cores showing low leakage degradation.

公开(公告)号：US20220407337A1

公开(公告)日：2022-12-22

申请号：US17354944

申请日：2021-06-22

Applicant: Intel Corporation

Inventor： Zhongsheng Wang ,  Chee Lim Nge ,  Sze Ling Yeap ,  Efraim Rotem ,  James Hermerding II ,  Ashraf Wadaa

IPC: H02J7/00

Abstract: A hardware and/or software (e.g., a controller and/or firmware or software) that monitors a remaining capacity of a battery and adjusts a continuum of system performance settings ranging from best performance to best energy efficiency. The controller starts with best performance setting (at the expense of energy efficiency), and then the controller gradually shifts toward energy efficiency setting (at the expense of performance) when a battery usage exceeds a pre-defined drain rate (e.g., there is a deficit in the battery remaining capacity until the next charge). The controller reverts from energy efficiency setting towards high performance setting when the battery drain rate or discharge rate slows down (e.g., there is a surplus in the battery remaining capacity until the next charge).

公开(公告)号：US11354213B2

公开(公告)日：2022-06-07

申请号：US16647563

申请日：2018-08-27

Applicant: Intel Corporation

Inventor： Hisham Abu Salah ,  Arthur Leonard Brown ,  Russell J. Fenger ,  Deepak Samuel Kirubakaran ,  Asit K. Mallick ,  Jun Pan ,  Srinivas Pandruvada ,  Efraim Rotem ,  Arjan Van De Ven ,  Eliezer Weissmann ,  Rafal J. Wysocki

IPC: G06F9/46 ,  G06F11/34 ,  G06F11/30 ,  G06F9/48 ,  G06F9/50

Abstract: In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to: maintain a first utilization metric for a first processing engine; detect a thread transfer from a first processing engine to a second processing engine; and generate, using the first utilization metric for the first processing engine, a second utilization metric for a second processing engine. Other embodiments are described and claimed.

公开(公告)号：US11243768B2

公开(公告)日：2022-02-08

申请号：US16259880

申请日：2019-01-28

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Boris Ginzburg ,  Alon Naveh ,  Nadav Shulman ,  Ronny Ronen

IPC: G06F11/34 ,  G06F11/30 ,  G06F9/30 ,  G06F9/38 ,  G06F9/455 ,  G06F1/3234

Abstract: Disclosed embodiments relate to processing logic for performing function operations. In one example, and apparatus includes an execution unit within a processor to execute a code block, power management hardware coupled to the execution unit, wherein the power management hardware is to monitor a first execution of the code block, store a micro-architectural context of the processor in a metadata block associated with the code block, the micro-architectural context including performance data resulting from the first execution of the code block, the performance data comprising power and energy usage data, and power management related parameters, read the associated metadata block upon a second execution of the code block, and tune the second execution based on the performance data stored in the associated metadata block to increase efficiency of executing the code block.

公开(公告)号：US11188138B2

公开(公告)日：2021-11-30

申请号：US16206019

申请日：2018-11-30

Applicant: Intel Corporation

Inventor： Michael Bitan ,  Andrey Gabdulin ,  Efraim Rotem ,  Eli Efron ,  Nadav Shulman ,  David Ben Shimon ,  Nir Levitin ,  Esfir Natanzon

IPC: G06F1/3296 ,  G06F1/324 ,  G06F1/20

Abstract: In an embodiment, a processor includes a plurality of processing engines to execute instructions and a power management unit. The power management unit is to: control an operating frequency and a supply voltage according to a first voltage/frequency curve associated with a first temperature; and in response to a detection of a second temperature in the processor, increase the operating frequency to a second frequency based on a second voltage/frequency curve, wherein, at least one voltage of a first range of voltages, the second voltage/frequency curve specifies a higher frequency than the first voltage/frequency curve. Other embodiments are described and claimed.

公开(公告)号：US11054877B2

公开(公告)日：2021-07-06

申请号：US16012623

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Dorit Shapira ,  Anand K. Enamandram ,  Daniel Cartagena ,  Krishnakanth Sistla ,  Jorge P. Rodriguez ,  Efraim Rotem ,  Nir Rosenzweig

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/324 ,  G06F1/3234 ,  H03M1/12

Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first sensing system to measure first power consumed by first one or more components of the plurality of components; a second sensing system to measure second power consumed by the apparatus; an analog-to-digital converter (ADC) to generate an identification (ID) that is representative of the second power consumed by the apparatus; and a controller to allocate power budget to one or more components of the plurality of components, based on the measurement of the first power and the ID.

公开(公告)号：US20210200293A1

公开(公告)日：2021-07-01

申请号：US17202765

申请日：2021-03-16

Applicant: Intel Corporation

Inventor： Hisham Abu Salah ,  Efraim Rotem ,  Eliezer Weissmann ,  Yoni Aizik ,  Daniel D. Lederman

IPC: G06F1/324 ,  G06F1/3296 ,  G06F1/3206

Abstract: In one embodiment, processor includes a first core to execute instructions, and a power controller to control power consumption of the processor. The power controller may include a hardware performance state controller to control a performance state of the first core autonomously to an operating system, and calculate a target operating frequency for the performance state based at least in part on an energy performance preference hint received from the operating system. Other embodiments are described and claimed.