公开(公告)号：US11979177B2

公开(公告)日：2024-05-07

申请号：US17810845

申请日：2022-07-06

Applicant: Intel Corporation

Inventor： Elan Banin ,  Eytan Mann ,  Rotem Banin ,  Ronen Gernizky ,  Ofir Degani ,  Igal Kushnir ,  Shahar Porat ,  Amir Rubin ,  Vladimir Volokitin ,  Elinor Kashani ,  Dmitry Felsenstein ,  Ayal Eshkoli ,  Tal Davidson ,  Eng Hun Ooi ,  Yossi Tsfati ,  Ran Shimon

IPC: H04B1/04 ,  H04L7/033

CPC classification number: H04B1/04 ,  H04L7/0331

Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

公开(公告)号：US11870449B2

公开(公告)日：2024-01-09

申请号：US17638739

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： Elan Banin ,  Yaniv Cohen ,  Ofir Degani ,  Igal Kushnir

IPC: H03L7/099 ,  G06F1/08 ,  H03L7/093

CPC classification number: H03L7/0992 ,  G06F1/08 ,  H03L7/093

Abstract: A clock generator calibration system can include a phased-locked loop and a correction circuit. The PLL can generate an output clock signal, and the correction circuit can adjust a frequency signal of the PLL based on a digital signal of the PLL. The digital signal can be generated based on the adjusted frequency signal.

公开(公告)号：US20210367629A1

公开(公告)日：2021-11-25

申请号：US17393564

申请日：2021-08-04

Applicant: Intel Corporation

Inventor： Ashoke Ravi ,  Benjamin Jann ,  Satwik Patnaik ,  Alexandros Margomenos ,  Igal Kushnir ,  Elan Banin ,  Ofir Degani

IPC: H04B1/04 ,  H03L7/24 ,  G01R27/06 ,  H01Q3/40

Abstract: Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.

公开(公告)号：US20210067182A1

公开(公告)日：2021-03-04

申请号：US16550574

申请日：2019-08-26

Applicant: Intel Corporation

Inventor： Ashoke Ravi ,  Jann Benjamin ,  Satwik Patnaik ,  Elan Banin ,  Igal Kushnir ,  Ofir Degani ,  Alexandros Margomenos

IPC: H04B1/04 ,  H01Q3/40 ,  G01R27/06 ,  H03L7/24

Abstract: Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.

公开(公告)号：US10804911B2

公开(公告)日：2020-10-13

申请号：US16292717

申请日：2019-03-05

Applicant: Intel Corporation

Inventor： Gil Horovitz ,  Sharon Malevsky ,  Evgeny Shumaker ,  Igal Kushnir

IPC: H03L7/099 ,  H04B1/00

Abstract: Systems, methods, and circuitries are provided to generate a radio frequency (RF) signal having a desired radio frequency fRF. In one example a frequency synthesizer system includes a clock, an opportunistic phase locked loop (PLL), and an RF PLL. The clock circuitry is configured to generate a clock signal having a frequency fXTL. The opportunistic phase locked loop (PLL) is configured to generate a reference signal having a reference frequency fREF that is close to a free-running frequency of an oscillator in the opportunistic PLL. The opportunistic PLL is configured to synchronize the reference signal to the clock signal. The RF PLL is configured to generate the RF signal having the desired radio frequency and to synchronize the RF signal with the reference signal.