公开(公告)号：US20240305769A1

公开(公告)日：2024-09-12

申请号：US18665184

申请日：2024-05-15

Applicant: Intel Corporation

Inventor： Jason Daniel Tanner ,  James Holland ,  Stanley Jacob Baran ,  Satya Yedidi ,  Penne Yat-Pei Lee ,  Sumit Bhatia

IPC: H04N19/103 ,  H04N19/136 ,  H04N19/172 ,  H04N19/177

CPC classification number: H04N19/103 ,  H04N19/136 ,  H04N19/172 ,  H04N19/177

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed of adaptive configurations of video encoder preset modes. An example apparatus comprising interface circuitry to obtain a video to be encoded, instructions, and at least one processor circuit to be programmed by the instructions to configure a video encoder to encode a first frame of the video based on a first preset mode of a plurality of preset modes associated respectively with a plurality of different relative encoder performance targets, select a second preset mode of the plurality of preset modes based on one or more characteristics associated with a second frame of the video, the second preset mode different from the first preset mode, and configure the video encoder to encode the second frame based on the second preset mode.

公开(公告)号：US11861761B2

公开(公告)日：2024-01-02

申请号：US17095590

申请日：2020-11-11

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Durgaprasad Bilagi ,  Joydeep Ray ,  Scott Janus ,  Sanjeev Jahagirdar ,  Brent Insko ,  Lidong Xu ,  Abhishek R. Appu ,  James Holland ,  Vasanth Ranganathan ,  Nikos Kaburlasos ,  Altug Koker ,  Xinmin Tian ,  Guei-Yuan Lueh ,  Changliang Wang

IPC: G06T1/60 ,  G06T1/20 ,  G06F12/0802 ,  G06N5/04

CPC classification number: G06T1/60 ,  G06F12/0802 ,  G06N5/04 ,  G06T1/20 ,  G06F2212/251

Abstract: Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a system includes a producer intellectual property (IP) (e.g., a media IP), a compute core (e.g., a GPU or an AI-specific core of the GPU), a streaming buffer logically interposed between the producer IP and the compute core. The producer IP is operable to consume data from memory and output results to the streaming buffer. The compute core is operable to perform AI inference processing based on data consumed from the streaming buffer and output AI inference processing results to the memory.

公开(公告)号：US20230260075A1

公开(公告)日：2023-08-17

申请号：US18305904

申请日：2023-04-24

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Durgaprasad Bilagi ,  Joydeep Ray ,  Scott Janus ,  Sanjeev Jahagirdar ,  Brent Insko ,  Lidong Xu ,  Abhishek R. Appu ,  James Holland ,  Vasanth Ranganathan ,  Nikos Kaburlasos ,  Altug Koker ,  Xinmin Tian ,  Guei-Yuan Lueh ,  Changliang Wang

IPC: G06T1/60 ,  G06T1/20 ,  G06F12/0802 ,  G06N5/04

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06F12/0802 ,  G06N5/04 ,  G06F2212/251

Abstract: Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a state of multiple intellectual property (IP) cores that have access to a common cache via a central fabric is observed. Responsive to the observed state being indicative of performance of a standalone workload by a first IP core of the multiple IP cores, the common cache is treated as a local cache of the first IP core by powering off the central fabric and causing the first IP core to access the common cache via a low power access path between the first IP core and the common cache that is outside of the central fabric.

公开(公告)号：US11049266B2

公开(公告)日：2021-06-29

申请号：US16050468

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： Scott Janus ,  Barnan Das ,  Hugues Labbe ,  Jong Dae Oh ,  Gokcen Cilingir ,  James Holland ,  Narayan Biswal ,  Yi-Jen Chiu ,  Qian Xu ,  Mayuresh Varerkar ,  Sang-Hee Lee ,  Stanley Baran ,  Srikanth Potluri ,  Jason Ross ,  Maruthi Sandeep Maddipatla

IPC: G06T7/262 ,  H04N19/436 ,  G06T3/40 ,  G06T15/08 ,  G06T17/00 ,  G06T7/30

Abstract: An apparatus comprises a processor to divide a first point cloud data set frame representing a three dimensional space at a first point in time into a matrix of blocks, determine at least one three dimensional (3D) motion vector for at least a subset of blocks in the matrix of blocks, generate a predicted second point cloud data set frame representing a prediction of the three dimensional space at a second point in time by applying the at least one 3D motion vector to the subset of blocks in the matrix of blocks, compare the predicted second point cloud data set frame to a second point cloud data set frame representing a prediction of the three dimensional space at a second point in time to generate a prediction error parameter, and encode the second point cloud data set frame as a function of the first point cloud data set frame and the at least one three dimensional (3D) motion vector when the prediction error factor is beneath an error threshold to produce an encoded second point cloud data set frame.

公开(公告)号：US20200043182A1

公开(公告)日：2020-02-06

申请号：US16050468

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： Scott Janus ,  Barnan Das ,  Hugues Labbe ,  Jong Dae Oh ,  Gokcen Cilingir ,  James Holland ,  Narayan Biswal ,  Yi-Jen Chiu ,  Qian Xu ,  Mayuresh Varerkar ,  Sang-Hee Lee ,  Stanley Baran ,  Srikanth Potluri ,  Jason Ross ,  Maruthi Sandeep Maddipatla

IPC: G06T7/262 ,  G06T3/40 ,  G06T7/30 ,  G06T15/08 ,  G06T17/00

Abstract: Embodiments described herein provide an apparatus comprising a processor to divide a first point cloud data set frame representing a three dimensional space at a first point in time into a matrix of blocks, determine at least one three dimensional (3D) motion vector for at least a subset of blocks in the matrix of blocks, generate a predicted second point cloud data set frame representing a prediction of the three dimensional space at a second point in time by applying the at least one 3D motion vector to the subset of blocks in the matrix of blocks, compare the predicted second point cloud data set frame to a second point cloud data set frame representing a prediction of the three dimensional space at a second point in time to generate a prediction error parameter, and encode the second point cloud data set frame as a function of the first point cloud data set frame and the at least one three dimensional (3D) motion vector when the prediction error factor is beneath an error threshold to produce an encoded second point cloud data set frame. Other embodiments may be described and claimed.

公开(公告)号：US20190200039A1

公开(公告)日：2019-06-27

申请号：US16292808

申请日：2019-03-05

Applicant: Intel Corporation

Inventor： Jason Tanner ,  Srinivasan Embar Raghukrishnan ,  James Holland

IPC: H04N19/567 ,  H04N19/159 ,  H04N19/105 ,  H04N19/46 ,  H04N19/176

CPC classification number: H04N19/567 ,  H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/46

Abstract: An embodiment of a motion estimator apparatus may include technology to receive a compound message, and perform rate distortion estimation and check refinement for two or more coding unit descriptions for a source block based on the received compound message. Other embodiments are disclosed and claimed.