公开(公告)号：US12101498B2

公开(公告)日：2024-09-24

申请号：US17442056

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Jill Boyce ,  Lidong Xu

IPC: H04N19/46 ,  H04N19/136 ,  H04N19/146 ,  H04N19/167 ,  H04N19/172 ,  H04N19/42

CPC classification number: H04N19/46 ,  H04N19/136 ,  H04N19/146 ,  H04N19/167 ,  H04N19/172 ,  H04N19/42

Abstract: Embodiments of a video codec may include technology to derive a conformance point for a sub-region of coded pictures in a coded video sequence in the video data, group any combination of sub-pictures that form a rectangular region into a sub-picture set, and/or derive a level indicator corresponding to a sub-picture based on a level of the coded video sequence and a relative size of the coded picture and the sub-picture set. Other embodiments are disclosed and claimed.

公开(公告)号：US20240153033A1

公开(公告)日：2024-05-09

申请号：US18281947

申请日：2021-06-16

Applicant: Intel Corporation

Inventor： Chen Wang ,  Huan Dou ,  Sang-Hee Lee ,  Yi-Jen Chiu ,  Lidong Xu

IPC: G06T3/4053 ,  G06T3/4046 ,  G06T7/11 ,  G06T7/40

CPC classification number: G06T3/4053 ,  G06T3/4046 ,  G06T7/11 ,  G06T7/40 ,  G06T2207/10016 ,  G06T2207/20084 ,  G06V10/82

Abstract: A method, system, and article is directed to automatic content-dependent image processing algorithm selection.

公开(公告)号：US11432011B2

公开(公告)日：2022-08-30

申请号：US17121669

申请日：2020-12-14

Applicant: Intel Corporation

Inventor： Wenhao Zhang ,  Yi-Jen Chiu ,  Pieter Kapsenberg ,  Lidong Xu ,  Yu Han ,  Zhipin Apple Deng ,  Xiaoxia Cai

IPC: H04N19/60 ,  H04N19/96 ,  H04N19/91 ,  H04N19/122

Abstract: Systems, apparatus, articles, and methods are described including operations for size based transform unit context derivation.

公开(公告)号：US11323700B2

公开(公告)日：2022-05-03

申请号：US17107258

申请日：2020-11-30

Applicant: Intel Corporation

Inventor： James M. Holland ,  Srinivasan Embar Raghukrishnan ,  Zhijun Lei ,  Dmitry E. Ryzhov ,  Lidong Xu ,  Satya N. Yedidi

IPC: H04N19/11 ,  H04N19/533 ,  H04N19/159 ,  H04N19/176 ,  H04N19/88 ,  H04N19/70 ,  H04N19/593 ,  H04N19/33 ,  H04N19/12 ,  H04N19/60

Abstract: Example apparatus to encode video disclosed herein include an encoder to perform an intra search first stage based on source pixels of a source video frame to determine first intra candidates to predict a block of the source video frame. In disclosed examples, the encoder is also to perform an intra search second stage based on reconstructed pixels of neighboring blocks associated with the first intra candidates to determine a second intra candidate. In disclosed examples, the encoder is further to encode the block of the source video frame based on the second intra candidate.

公开(公告)号：US20210149763A1

公开(公告)日：2021-05-20

申请号：US17095530

申请日：2020-11-11

Applicant: Intel Corporation

Inventor： Vasanth Ranganathan ,  Joydeep Ray ,  Abhishek R. Appu ,  Nikos Kaburlasos ,  Lidong Xu ,  Subramaniam Maiyuran ,  Altug Koker ,  Naveen Matam ,  James Holland ,  Brent Insko ,  Sanjeev Jahagirdar ,  Scott Janus ,  Durgaprasad Bilagi ,  Xinmin Tian

IPC: G06F11/10 ,  G06F12/0802 ,  G06T1/20 ,  G06T1/60

Abstract: Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.

公开(公告)号：US20210149677A1

公开(公告)日：2021-05-20

申请号：US17095626

申请日：2020-11-11

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Lidong Xu ,  Abhishek R. Appu ,  James M. Holland ,  Vasanth Ranganathan ,  Nikos Kaburlasos ,  Altug Koker

IPC: G06F9/38 ,  G06F9/30 ,  G06F15/80 ,  G06K9/62 ,  G06N20/00

Abstract: Enhanced processor functions for calculation are described. An example of an apparatus includes one or more processors including one or more processing resources and a memory to store data, the data including data for compute operations. A processing resource of the one or more processing resources includes a configurable pipeline for calculation operations, and wherein the configurable pipeline may be utilized to perform both a normal instruction for a calculation in a certain precision and a systolic instruction for a calculation in a certain precision.

公开(公告)号：US20210084294A1

公开(公告)日：2021-03-18

申请号：US17107258

申请日：2020-11-30

Applicant: Intel Corporation

Inventor： James M. Holland ,  Srinivasan Embar Raghukrishnan ,  Zhijun Lei ,  Dmitry E. Ryzhov ,  Lidong Xu ,  Satya N. Yedidi

IPC: H04N19/11 ,  H04N19/533 ,  H04N19/159 ,  H04N19/176 ,  H04N19/88 ,  H04N19/70 ,  H04N19/593 ,  H04N19/33 ,  H04N19/12

Abstract: Example apparatus to encode video disclosed herein include an encoder to perform an intra search first stage based on source pixels of a source video frame to determine first intra candidates to predict a block of the source video frame. In disclosed examples, the encoder is also to perform an intra search second stage based on reconstructed pixels of neighboring blocks associated with the first intra candidates to determine a second intra candidate. In disclosed examples, the encoder is further to encode the block of the source video frame based on the second intra candidate.

公开(公告)号：US10855983B2

公开(公告)日：2020-12-01

申请号：US16440159

申请日：2019-06-13

Applicant: INTEL CORPORATION

Inventor： James M. Holland ,  Srinivasan Embar Raghukrishnan ,  Zhijun Lei ,  Dmitry E. Ryzhov ,  Lidong Xu ,  Satya N. Yedidi

IPC: H04N19/11 ,  H04N19/533 ,  H04N19/159 ,  H04N19/176 ,  H04N19/88 ,  H04N19/70 ,  H04N19/593 ,  H04N19/33 ,  H04N19/12 ,  H04N19/60

Abstract: An example system includes a processor to execute an intra search first stage on a video frame to generate intra candidates. The processor is to execute an intra search second stage on the intra candidates to generate a final intra candidate and residuals. The processor is to also execute a final mode decision and generate reconstructed pixels based on the final intra candidate and the residuals.

公开(公告)号：US20190387250A1

公开(公告)日：2019-12-19

申请号：US16437158

申请日：2019-06-11

Applicant: Intel Corporation

Inventor： Jill Boyce ,  Zhipin Deng ,  Lidong Xu

IPC: H04N19/523 ,  H04N19/573 ,  H04N19/543 ,  H04N19/52

Abstract: Embodiments are generally directed to affine motion compensation for current picture referencing. An embodiment of an apparatus includes one or more processors for processing of data; a memory for storage of data including video data; and an encoder for encoding of video data to generate encoded video data, wherein the encoder includes a component to provide affine motion compensation for current picture references in the video data.

公开(公告)号：US10477208B2

公开(公告)日：2019-11-12

申请号：US15459043

申请日：2017-03-15

Applicant: Intel Corporation

Inventor： Lidong Xu ,  Yi-Jen Chiu ,  Wenhao Zhang ,  Hong Jiang

IPC: H04N19/117 ,  H04N19/182 ,  H04N19/147 ,  H04N19/136

Abstract: Reconstructed picture quality for a video codec system may be improved by categorizing reconstructed pixels into different histogram bins with histogram segmentation and then applying different filters on different bins. Histogram segmentation may be performed by averagely dividing the histogram into M bins or adaptively dividing the histogram into N bins based on the histogram characteristics. Here M and N may be a predefined, fixed, non-negative integer value or an adaptively generated value at encoder side and may be sent to decoder through the coded bitstream.