公开(公告)号：US11652143B2

公开(公告)日：2023-05-16

申请号：US16367549

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Nidhi Nidhi ,  Paul B. Fischer ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Samuel Jack Beach ,  Xiaojun Weng ,  Johann Christian Rode ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/10 ,  H01L29/20 ,  H01L29/786 ,  H01L29/778 ,  H01L29/16 ,  H01L29/08 ,  H01L21/8238 ,  H01L27/07

CPC classification number: H01L29/1033 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/0705 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/778 ,  H01L29/78696

Abstract: Disclosed herein are IC structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N devices, e.g., III-N transistors. In various aspects, TFTs integrated with III-N transistors have a channel and source/drain materials that include one or more of a crystalline material, a polycrystalline semiconductor material, or a laminate of crystalline and polycrystalline materials. In various aspects, TFTs integrated with III-N transistors are engineered to include one or more of 1) graded dopant concentrations in their source/drain regions, 2) graded dopant concentrations in their channel regions, and 3) thicker and/or composite gate dielectrics in their gate stacks.

公开(公告)号：US11588037B2

公开(公告)日：2023-02-21

申请号：US16289824

申请日：2019-03-01

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Rahul Ramaswamy ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Johann Christian Rode ,  Paul B. Fischer ,  Walid M. Hafez

IPC: H01L29/423 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/778 ,  H01L23/66 ,  H01L23/498 ,  H01L21/28 ,  H01L29/66 ,  H01L23/00

Abstract: Disclosed herein are IC structures, packages, and devices that include planar III-N transistors with wrap-around gates and/or one or more wrap-around source/drain (S/D) contacts. An example IC structure includes a support structure (e.g., a substrate) and a planar III-N transistor. The transistor includes a channel stack of a III-N semiconductor material and a polarization material, provided over the support structure, a pair of S/D regions provided in the channel stack, and a gate stack of a gate dielectric material and a gate electrode material provided over a portion of the channel stack between the S/D regions, where the gate stack at least partially wraps around an upper portion of the channel stack.

公开(公告)号：US11587924B2

公开(公告)日：2023-02-21

申请号：US16362269

申请日：2019-03-22

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Rahul Ramaswamy ,  Han Wui Then ,  Marko Radosavljevic ,  Johann Christian Rode ,  Paul B. Fischer ,  Walid M. Hafez

IPC: H01L21/00 ,  H01L27/06 ,  H01L21/8252 ,  H01L27/01

Abstract: Disclosed herein are integrated circuit structures, packages, and devices that include resistors and/or capacitors which may be provided on the same substrate/die/chip as III-N devices, e.g., III-N transistors. An integrated circuit structure, comprising a base structure comprising a III-N material, the base structure having a conductive region of a doped III-N material. The IC structure further comprises a first contact element, including a first conductive element, a dielectric element, and a second conductive element, wherein the dielectric element is between the first conductive element and the second conductive element, and wherein the first conductive element is between the conductive region and the dielectric element. The IC structure further comprises a second contact element electrically coupled to the first contact element via the conductive region.

公开(公告)号：US20220068910A1

公开(公告)日：2022-03-03

申请号：US17007165

申请日：2020-08-31

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Johann Christian Rode ,  Rahul Ramaswamy ,  Marko Radosavljevic ,  Nidhi Nidhi ,  Walid M. Hafez ,  Paul B. Fischer ,  Sansaptak Dasgupta

IPC: H01L27/06 ,  H01L27/092 ,  H01L29/20 ,  H01L29/205 ,  H01L29/861 ,  H01L29/778

Abstract: Disclosed herein are IC structures, packages, and devices that include linearization devices integrated on the same support structure as III-N transistors. A linearization device may be any suitable device that may exhibit behavior complementary to that of a III-N transistor so that a combined behavior of the III-N transistor and the linearization device includes less nonlinearity than the behavior of the III-N transistor alone. Linearization devices may be implemented as, e.g., one-sided diodes, two-sided diodes, or P-type transistors. Integrating linearization devices on the same support structure with III-N transistors advantageously provides an integrated solution based on III-N transistor technology, thus providing a viable approach to reducing or eliminating nonlinear behavior of III-N transistors. In some implementations, linearization devices may be integrated with III-N transistors by being disposed side-by-side with the III-N transistors, advantageously enabling implementation of both the III-N transistors and the linearization devices in a single device layer.

公开(公告)号：US20200294932A1

公开(公告)日：2020-09-17

申请号：US16354241

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Nidhi Nidhi ,  Paul B. Fischer ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Johann Christian Rode

IPC: H01L23/552 ,  H01L29/778 ,  H01L29/207 ,  H01L29/66

Abstract: IC structures that include transmission line structures to be integrated with III-N devices are disclosed. An example transmission line structure includes a transmission line of an electrically conductive material provided above a stack of a III-N semiconductor material and a polarization material. The transmission line structure further includes means for reducing electromagnetic coupling between the line and charge carriers present below the interface of the polarization material and the III-N semiconductor material. In some embodiments, said means include a shield material of a metal or a doped semiconductor provided over portions of the polarization material that are under the transmission line. In other embodiments, said means include dopant atoms implanted into the portions of the polarization material that are under the transmission line, and into at least an upper portion of the III-N semiconductor material under such portions of the polarization material.

公开(公告)号：US20200273860A1

公开(公告)日：2020-08-27

申请号：US16283301

申请日：2019-02-22

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Johann Christian Rode ,  Han Wui Then ,  Marko Radosavljevic ,  Paul B. Fischer ,  Nidhi Nidhi ,  Rahul Ramaswamy ,  Sandrine Charue-Bakker ,  Walid M. Hafez

IPC: H01L27/092 ,  H01L29/267 ,  H01L21/8258

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same support structure as non-III-N transistors (e.g., Si-based transistors), using semiconductor regrowth. In one aspect, a non-III-N transistor may be integrated with an III-N transistor by depositing a III-N material, forming an opening in the III-N material, and epitaxially growing within the opening a semiconductor material other than the III-N material. Since the III-N material may serve as a foundation for forming III-N transistors, while the non-III-N material may serve as a foundation for forming non-III-N transistors, such an approach advantageously enables implementation of both types of transistors on a single support structure. Proposed integration may reduce costs and improve performance by enabling integrated digital logic solutions for III-N transistors and by reducing losses incurred when power is routed off chip in a multi-chip package.

公开(公告)号：US20200266291A1

公开(公告)日：2020-08-20

申请号：US16275631

申请日：2019-02-14

Applicant: Intel Corporation

Inventor： Johann Christian Rode ,  Nidhi Nidhi ,  Rahul Ramaswamy ,  Han Wui Then ,  Walid M. Hafez

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/66

Abstract: Disclosed herein are IC structures that implement field plates for III-N transistors in a form of electrically conductive structures provided in a III-N semiconductor material below the polarization layer (i.e., at the “backside” of an IC structure). In some embodiments, such a field plate may be implemented as a through-silicon via (TSV) extending from the back/bottom face of the substrate towards the III-N semiconductor material. Implementing field plates at the backside may provide a viable approach to changing the distribution of electric field at a transistor drain and increasing the breakdown voltage of an III-N transistor without incurring the large parasitic capacitances associated with the use of metal field plates provided above the polarization material. In addition, backside field plates may serve as a back barrier for advantageously reducing drain-induced barrier lowering.

公开(公告)号：US20200219986A1

公开(公告)日：2020-07-09

申请号：US16242670

申请日：2019-01-08

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Glenn A. Glass ,  Sansaptak Dasgupta ,  Nidhi Nidhi ,  Paul B. Fischer ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Johann Christian Rode

IPC: H01L29/40 ,  H01L29/778 ,  H01L21/265

Abstract: Disclosed herein are IC structures, packages, and devices assemblies that use ions or fixed charge to create field plate structures which are embedded in a dielectric material between gate and drain electrodes of a transistor, ion- or fixed charge-based field plate structures may provide viable approaches to changing the distribution of electric field at a transistor drain to increase the breakdown voltage of a transistor without incurring the large parasitic capacitances associated with the use of metal field plates. In one aspect, an IC structure includes a transistor, a dielectric material between gate and drain electrodes of the transistor, and an ion- or fixed charge-based region within the dielectric material, between the gate and the drain electrodes. Such an ion- or fixed charge-based region realizes an ion- or fixed charge-based field plate structure. Optionally, the IC structure may include multiple ion- or fixed charge-based field plate structures.