公开(公告)号：US20180095883A1

公开(公告)日：2018-04-05

申请号：US15283337

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Leon Polishuk ,  Pavel Konev ,  Larisa Novakovsky ,  Julius Mandelblat

IPC: G06F12/0866 ,  G06F9/44

CPC classification number: G06F9/4401 ,  G06F12/126

Abstract: Systems and methods are disclosed for initialization of a processor. Embodiments relate to alleviating any BIOS code size limitation. In one example, a system includes a memory having stored thereon a basic input/output system (BIOS) program comprising a readable code region and a readable and writeable data stack, a circuit coupled to the memory and to: read, during a boot mode and while using a cache as RAM (CAR), at least one datum from each cache line of the data stack, and write at least one byte of each cache line of the data stack to set a state of each cache line of the data stack to modified, enter a no-modified-data-eviction mode to protect modified data from eviction, and to allow eviction and replacement of readable data, and begin reading from the readable code region and executing the BIOS program after entering the no-modified-data-eviction mode.