公开(公告)号：US20200349312A1

公开(公告)日：2020-11-05

申请号：US16854788

申请日：2020-04-21

Applicant: Intel Corporation

Inventor： Tsvika Kurts ,  Alexander Gendler ,  Larisa Novakovsky ,  Anwar Azaarura Zaa'Rura ,  Afik Sela ,  Genadi Kazakevich ,  Alexandra Shainshein ,  Ariel Sabba

IPC: G06F30/3323 ,  G01R31/317 ,  G06F11/30 ,  G06F11/34 ,  G06F11/36

Abstract: An apparatus, including: a deterministic monitored device; an interconnect to communicatively couple the monitored device to a support circuit; a super queue to queue transactions between the monitored device and the support circuit, the super queue including an operational segment and a shadow segment; a debug data structure; and a system management agent to monitor transactions in the operational segment, log corresponding transaction identifiers in the shadow segment, and write debug data to the debug data structure, wherein the debug data are at least partly based on the corresponding transaction identifiers.

公开(公告)号：US20200096569A1

公开(公告)日：2020-03-26

申请号：US16142591

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Michael Mishaeli ,  Larisa Novakovsky ,  Edward Brazil ,  Alexander Gendler

IPC: G01R31/3185 ,  G06F1/32 ,  G01R31/319

Abstract: In one embodiment, a processor includes a scan system controller to control test operations on the processor in response to test commands from an external test entity, and at least one core to execute instructions. The processor may further include a field scan controller to control a field test mode of the processor to perform a self-test of the at least one core during field operation, where the field scan controller is to obtain a test pattern from an external memory and cause the scan system controller to test circuitry of the first subsystem using the test pattern. Other embodiments are described and claimed.

公开(公告)号：US20190243701A1

公开(公告)日：2019-08-08

申请号：US15890893

申请日：2018-02-07

Applicant: Intel Corporation

Inventor： Tsvika Kurts ,  Ki W. Yoon ,  Michael J. St. Clair ,  Larisa Novakovsky ,  Hisham Shafi ,  William H. Penner ,  Yoni Aizik ,  Kevin Safford ,  Hermann Gartler

IPC: G06F11/07 ,  G06F9/38

Abstract: Embodiment of this disclosure provides a mechanism to support hang detection and data recovery in microprocessor systems. In one embodiment, a processing device comprising a processing core and a crashlog unit operatively coupled to the core is provided. An indication of an unresponsive state in an execution of a pending instruction by the core is received. Responsive to receiving the indication, a crash log comprising data from registers of at least one of: a core region, a non-core region and a controller hub associated with the processing device is produced. Thereupon, the crash log is stored in a shared memory of a power management controller (PMC) associated with the controller hub.

公开(公告)号：US09471494B2

公开(公告)日：2016-10-18

申请号：US14137432

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  Neil M. Schaper ,  Joseph Nuzman ,  Larisa Novakovsky ,  Yen-Cheng Liu ,  Gilbert Neiger ,  Raj K. Ramanujan

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0831 ,  G06F2212/1032 ,  G06F2212/222

Abstract: An apparatus and method are described for performing a cache line write back operation. For example, one embodiment of a method comprises: initiating a cache line write back operation directed to a particular linear address; determining if a dirty cache line identified by the linear address exists at any cache of a cache hierarchy comprised of a plurality of cache levels; writing back the dirty cache line to memory if the dirty cache line exists in one of the caches; and responsively maintaining or placing the dirty cache line in an exclusive state in at least a first cache of the hierarchy.

Abstract translation: 描述了用于执行高速缓存行回写操作的装置和方法。 例如，方法的一个实施例包括：发起针对特定线性地址的高速缓存行回写操作; 确定由线性地址识别的脏高速缓存行是否存在于由多个高速缓存级别组成的高速缓存层级的任何高速缓存上; 如果脏缓存行存在于其中一个缓存中，则将脏缓存行写回内存; 以及响应地将所述脏高速缓存行维持或置于所述层次结构的至少第一高速缓存中的排他状态。

公开(公告)号：US08990512B2

公开(公告)日：2015-03-24

申请号：US13664682

申请日：2012-10-31

Applicant: Intel Corporation

Inventor： Stanislav Shwartsman ,  Raanan Sade ,  Larisa Novakovsky ,  Arijit Biswas

IPC: G06F12/00

CPC classification number: G06F12/121 ,  G06F11/1064 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084 ,  G06F2212/1032 ,  G06T1/20

Abstract: A processor includes a core to execute instructions and a cache memory coupled to the core and having a plurality of entries. Each entry of the cache memory may include a data storage including a plurality of data storage portions, each data storage portion to store a corresponding data portion. Each entry may also include a metadata storage to store a plurality of portion modification indicators, each portion modification indicator corresponding to one of the data storage portions. Each portion modification indicator is to indicate whether the data portion stored in the corresponding data storage portion has been modified, independently of cache coherency state information of the entry. Other embodiments are described as claimed.

Abstract translation: 处理器包括执行指令的核心和耦合到核心并且具有多个条目的高速缓存存储器。 高速缓冲存储器的每个条目可以包括包括多个数据存储部分的数据存储部分，每个数据存储部分存储对应的数据部分。 每个条目还可以包括用于存储多个部分修改指示符的元数据存储器，每个部分修改指示符对应于数据存储部分之一。 每个部分修改指示符用于指示存储在相应的数据存储部分中的数据部分是否已被修改，而与条目的高速缓存一致性状态信息无关。 其他实施例被描述为所要求保护的。

公开(公告)号：US20230315630A1

公开(公告)日：2023-10-05

申请号：US17708435

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Hanna Alam ,  Yuval Bustan ,  Tomer Exterman ,  Dor Kahana ,  Larisa Novakovsky ,  Joseph Nuzman

IPC: G06F12/0811

CPC classification number: G06F12/0811 ,  G06F2212/62

Abstract: Methods and apparatus relating to a dynamic inclusive and non-inclusive caching policy are described. In an embodiment, a first cache has a higher level than a second cache. Circuitry determines a caching policy between the first cache and the second cache based on a comparison of a number of active processor cores and a threshold value. The caching policy is one of an inclusive caching policy or a non-inclusive caching policy. Other embodiments are also disclosed and claimed.

公开(公告)号：US10157136B2

公开(公告)日：2018-12-18

申请号：US15087917

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Leeor Peled ,  Joseph Nuzman ,  Larisa Novakovsky

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/0862 ,  G06F12/0897

Abstract: A processor includes a front end to decode instructions, an execution unit to execute instructions, multiple caches at different cache hierarchy levels, a pipelined prefetcher, and a retirement unit to retire instructions. The prefetcher includes circuitry to receive a demand request for data at a first address within a first line in a memory and, in response, to provide the data at the first address to the execution unit for consumption, to prefetch a second line at a first offset distance from the first line into a mid-level cache, and to prefetch a third line at a second offset distance from the second line into a last-level cache. The prefetcher includes circuitry to prefetch, in response to another demand request, the third line into the mid-level cache, and a fourth line into the last-level cache. The prefetcher enforces minimum or maximum offset distances between prefetched data streams.

公开(公告)号：US20180181401A1

公开(公告)日：2018-06-28

申请号：US15886313

申请日：2018-02-01

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Larisa Novakovsky ,  Ariel Szapiro

IPC: G06F9/38 ,  G06F1/32 ,  G06F1/26

CPC classification number: G06F9/3802 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  G06F9/3881 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20

Abstract: In one embodiment, a processor includes: a core to execute instructions, the core including a plurality of mailbox storages and a trust table to store a trust indicator for each of the plurality of mailbox storages; a first core perimeter logic coupled to the core and including a first storage to store state information of the core when the core is in a low power state; and a second core perimeter logic coupled to the first core perimeter logic and the core, the second core perimeter logic including a second storage to store the state information of the core when the first core perimeter logic is in a low power state. Other embodiments are described and claimed.

公开(公告)号：US09535476B2

公开(公告)日：2017-01-03

申请号：US14497549

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Shani Rehana ,  Alexander Gendler ,  Larisa Novakovsky

IPC: G06F1/12 ,  G06F3/06 ,  G06F5/06 ,  G06F1/26 ,  G06F5/10

CPC classification number: G06F1/26 ,  G06F1/12 ,  G06F3/0656 ,  G06F5/10 ,  G06F15/17331

Abstract: In an embodiment, a processor includes a first domain to operate according to a first clock. The first domain includes a write source, a payload bubble generator first in first out buffer (payload BGF) to store data packets, and write credit logic to maintain a count of write credits. The processor also includes a second domain to operate according to a second clock. When the write source has a data packet to be stored while the second clock is shut down, the write source is to write the data packet to the payload BGF responsive to the count of write credits being at least one, and after the second clock is restarted the second domain is to read the data packet from the payload BGF. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括根据第一时钟进行操作的第一域。 第一域包括首先在先出缓冲器（有效载荷BGF）中存储数据分组的写入源，有效负载气泡生成器，以及写入信用逻辑以维持写入信用的计数。 处理器还包括第二域，以便按照第二时钟进行操作。 当写入源具有在第二时钟关闭时要存储的数据包时，写入源将数据包写入有效载荷BGF，响应于至少一个写入信用的计数，并且在第二个时钟为 重新启动第二个域是从有效载荷BGF读取数据包。 描述和要求保护其他实施例。

公开(公告)号：US09471088B2

公开(公告)日：2016-10-18

申请号：US13925986

申请日：2013-06-25

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Efraim Rotem ,  Julius Mandelblat ,  Alexander Lyakhov ,  Larisa Novakovsky ,  George Leifman ,  Lev Makovsky ,  Ariel Sabba ,  Niv Tokman

IPC: G06F1/08 ,  G06F1/04 ,  G06F1/32

CPC classification number: G06F1/08 ,  G06F1/04 ,  G06F1/32

Abstract: In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a restriction command and to reduce delivery of the first clock signal to at least one of the plurality of units. The restriction logic may cause the first clock signal to be distributed to the plurality of units at a lower frequency than a frequency of the first clock signal. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括用于执行指令的核心，其中核心包括时钟生成逻辑，用于接收和分配第一时钟信号到核心的多个单元，用于接收限制命令并减少传送的限制逻辑 的第一时钟信号发送到多个单元中的至少一个。 限制逻辑可以使得第一时钟信号以比第一时钟信号的频率低的频率被分配到多个单元。 描述和要求保护其他实施例。