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21.发明授权公开(公告)号：US11940824B2
公开(公告)日：2024-03-26
申请号：US17100603
申请日：2020-11-20
Applicant: Intel Corporation
Inventor： Xiaosen Liu , Harish Krishnamurthy , Krishnan Ravichandran , Vivek De , Scott Chiu , Claudia Patricia Barrera Gonzalez , Jing Han , Rajasekhara Madhusudan Narayana Bhatla
Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.
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公开(公告)号：US11444532B2
公开(公告)日：2022-09-13
申请号：US16727759
申请日：2019-12-26
Applicant: Intel Corporation
Inventor： Xiaosen Liu , Krishnan Ravichandran , Harish Krishnamurthy , Vivek De
Abstract: A 3-level ripple quantization scheme provides power transistor (MOS) strength-tuning mechanism focused on the transient clamp period. The 3-level ripple quantization scheme solves the digital low dropout's (D-LDO's) tradeoff between silicon area (e.g., decoupling capacitor size), quiescent power consumption (e.g., speed of comparators), wide load range, and optimal output ripple. The 3-level ripple quantization scheme eliminates oscillation risk from either wide dynamic range or parasitic by exploiting asynchronous pulse patterns. As such, ripple magnitude for both fast di/dt loading events and various steady-state scenarios are shrunk effectively, resulting significant efficiency benefits.
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23.发明授权公开(公告)号：US10897364B2
公开(公告)日：2021-01-19
申请号：US15846045
申请日：2017-12-18
Applicant: Intel Corporation
Inventor： Vivek De , Krishnan Ravichandran , Harish Krishnamurthy , Khondker Ahmed , Sriram Vangal , Vaibhav Vaidya , Turbo Majumder , Christopher Schaef , Suhwan Kim , Xiaosen Liu , Nachiket Desai
IPC: H04L9/32
Abstract: Spin Hall Effect (SHE) magneto junction memory cells (e.g., magnetic tunneling junction (MTJ) or spin valve based memory cells) are used to implement high entropy physically unclonable function (PUF) arrays utilizing stochastics interactions of both parameter variations of the SHE-MTJ structures as well as random thermal noises. An apparatus is provided which comprises: an array of PUF devices, wherein an individual device of the array comprises a magnetic junction and an interconnect, wherein the interconnect comprises a spin orbit coupling material; a circuitry to sense values stored in the array, and to provide an output; and a comparator to compare the output with a code.
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24.发明申请公开(公告)号：US20190317536A1
公开(公告)日：2019-10-17
申请号：US16450873
申请日：2019-06-24
Applicant: Intel Corporation
Inventor： Xiaosen Liu , Harish Krishnamurthy , Krishnan Ravichandran , Vivek De , Scott Chiu , Claudia Patricia Barrera Gonzalez , Jing Han , Rajasekhara Madhusudan Narayana Bhatla
Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.
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公开(公告)号：US09819266B2
公开(公告)日：2017-11-14
申请号：US14757732
申请日：2015-12-23
Applicant: Intel Corporation
Inventor： Vaibhav Vaidya , Vivek K. De , Krishnan Ravichandran
IPC: H02M3/158
CPC classification number: H02M3/158 , H02M1/083 , H02M3/1588 , Y02B70/1466
Abstract: Generally, this disclosure describes an apparatus. The apparatus includes switch controller circuitry and zero crossing logic circuitry. The switch controller circuitry is to control a conduction state of a high side switch and a low side switch in a DC to DC converter. The zero crossing logic circuitry includes phase comparator circuitry, a first clocking circuitry and a second clocking circuitry. Each clocking circuitry includes one or more delay elements. The zero crossing logic circuitry is to monitor a switch node voltage, Vsw, and to determine whether Vsw is greater than a reference, Vref. The switch controller circuitry is to turn off a low side switch if Vsw is greater than Vref while the low side switch is turned on, Vsw greater than Vref corresponding to a negative inductor current.
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Patent Agency Ranking
公开(公告)号：US20170179733A1
公开(公告)日：2017-06-22
申请号：US14976210
申请日：2015-12-21
Applicant: INTEL CORPORATION
Inventor： Naoki Matsumura , Andrew W. Keates , Krishnan Ravichandran
CPC classification number: H02J7/35 , H02J7/0047 , H02J7/0063 , H02J7/008 , H02J2007/005 , H02J2007/0067
Abstract: A system for increasing the life of a battery cell by limiting the charging of the battery to less than full charge in response to a predicted electricity draw of a connected device being less than the full capacity of the battery before a predicted recharge will occur. The current draw of the connected device may be affected by the amount of time before a next recharge and environmental factors. The system may further comprise one or more sensors to gather data pertaining to environmental conditions that may be used in the calculation of a charge termination value. The charge termination value is an amount of charge to power the device for a duration of time at least until a predicted recharge begins.
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公开(公告)号：US09600060B2
公开(公告)日：2017-03-21
申请号：US14506465
申请日：2014-10-03
Applicant: Intel Corporation
Inventor： Bradley Saunders , Krishnan Ravichandran
CPC classification number: G06F1/3278 , G06F1/325 , G06F1/3253 , G06F13/42 , Y02D10/151 , Y02D10/157
Abstract: Described are embodiments of methods, apparatuses, and systems for link power management in an I/O interconnect. An apparatus for link power management in an I/O interconnect of a computer apparatus may include a switching fabric having a first switch and a second switch, configured to simultaneously transport first data packets over a first path of a link between a port of the first switch and a port of the second switch and second data packets over a second path of the link. The apparatus may include a power management unit configured to modify a power state of the port of the first switch based at least in part on relative power states of the first path and the second path. Other embodiments may be described and claimed.
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公开(公告)号：US09281699B2
公开(公告)日：2016-03-08
申请号：US13728227
申请日：2012-12-27
Applicant: INTEL CORPORATION
Inventor： Lilly Huang , Wayne L. Proefrock , Krishnan Ravichandran
IPC: H02J7/00
CPC classification number: H02J7/0042 , H02J7/35
Abstract: A mobile device may be provided that includes an input port, an adjusting device, and a voltage regulator. The input port may receive power from an alternative power source or a DC power supply. The mobile device may receive the power from the input port, adjust a power characteristic of the power, and provide the power having the adjusted power characteristic. The voltage regulator may receive the adjusted power and provide a regulated voltage to a load.
Abstract translation: 可以提供包括输入端口，调节装置和电压调节器的移动装置。 输入端口可以从替代电源或直流电源接收电力。 移动设备可以从输入端口接收电力，调整功率的功率特性，并提供具有调整的功率特性的功率。 电压调节器可以接收经调整的功率并向负载提供调节电压。
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29.发明授权Apparatus, method, and system for improved power delivery performance with a dynamic voltage pulse scheme 有权用动态电压脉冲方案提高功率输送性能的装置，方法和系统公开(公告)号：US09037883B2
公开(公告)日：2015-05-19
申请号：US14020364
申请日：2013-09-06
Applicant: Intel Corporation
Inventor： Lilly Huang , Krishnan Ravichandran
Abstract: An apparatus and method is described herein for providing a dynamic pulse scheme for a voltage supply. A load (current) demand event of a processor is either predicted and/or detected. In response to the current demand event, such as a change in the current demand; a temporary, transient voltage pulse is generated by a voltage supply to compensate for the current transient demand. As result, dynamic voltage supply pulses generated based on the load current or the prediction of the load current demand increases performance, decreases power consumption, and saves expensive addition of compensation components, such as capacitors to a processor package.
Abstract translation: 这里描述了一种用于提供用于电压源的动态脉冲方案的装置和方法。 处理器的负载（当前）需求事件是预测和/或检测的。 针对目前的需求事件，如当前需求的变化; 由电压源产生临时的瞬态电压脉冲，以补偿电流瞬态需求。 结果，基于负载电流产生的动态电压供给脉冲或负载电流需求的预测增加了性能，降低了功耗，并且将诸如电容器的补偿组件的昂贵的添加节省到处理器封装中。
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公开(公告)号：US20220374060A1
公开(公告)日：2022-11-24
申请号：US17323837
申请日：2021-05-18
Applicant: Intel Corporation
Inventor： Harish K. Krishnamurthy , Xun Sun , Krishnan Ravichandran
Abstract: A computational current sensor, that enhances traditional Kalman filter based current observer techniques, with transient tracking enhancements and an online parasitic parameter identification that enhances overall accuracy during steady state and transient events while guaranteeing convergence. During transient operation (e.g., a voltage droop), a main filter is bypassed with estimated values calculated from a charge balance principle to enhance accuracy while tracking transient current surges of the DC-DC converter. To address the issue of dependency on a precise model parameter information and further improve accuracy, an online identification algorithm is included to track the equivalent parasitic resistance at run-time.
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