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    COMMAND PROCESSING FOR GRAPHICS TILE-BASED RENDERING
    22.
    发明申请
    COMMAND PROCESSING FOR GRAPHICS TILE-BASED RENDERING 审中-公开

    公开(公告)号：US20170337656A1

    公开(公告)日：2017-11-23

    申请号：US15159897

    申请日：2016-05-20

    Applicant: Intel Corporation

    Inventor： Balaji Vembu ,  Peter L. Doyle ,  Michael Apodaca ,  Hema C. Nalluri ,  Jeffery S. Boles

    IPC: G06T1/20 ,  G06T1/60 ,  G06T15/00 ,  G06T15/80

    CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T11/40 ,  G06T15/005 ,  G06T15/40 ,  G06T15/80

    Abstract: The same set of render commands can be re-executed for each of a plurality of tiles making up a graphic scene to be rendered. Each time the list of commands is executed, the way the commands are executed may be modified based on information received from tile pre-processing. Specifically, a jump if command may be inserted into the command list. When this command is encountered, a determination is made, based on information received from tile pre-processing pipeline, whether to execute the command for the next primitive or not. If the next primitive is to be culled then the command for the next primitive is not executed and the flow moves past that command. If the next primitive is to be executed then the jump is not implemented. This enables avoiding reloading the same list of commands over and over for every tile.

    FACILITATING DYNAMIC RUNTIME TRANSFORMATION OF GRAPHICS PROCESSING COMMANDS FOR IMPROVED GRAPHICS PERFORMANCE AT COMPUTING DEVICES
    23.
    发明申请
    FACILITATING DYNAMIC RUNTIME TRANSFORMATION OF GRAPHICS PROCESSING COMMANDS FOR IMPROVED GRAPHICS PERFORMANCE AT COMPUTING DEVICES 审中-公开
    促进图形处理命令的动态运行转换改进计算设备的图形性能

    公开(公告)号：US20160364828A1

    公开(公告)日：2016-12-15

    申请号：US14738679

    申请日：2015-06-12

    Applicant: INTEL CORPORATION

    Inventor： James A. Valerio ,  Abhishek Venkatesh ,  Satyajit Sarangi ,  Michael Apodaca ,  Thomas F. Raoux ,  Hashem Hashemi ,  Rama S.B. Harihara

    IPC: G06T1/20

    Abstract: A mechanism is described for facilitating dynamic runtime transformation of graphics processing commands for improved graphics performance on computing devices. A method of embodiments, as described herein, includes detecting a command stream associated with an application, where the command stream includes dispatches. The method may further include evaluating processing parameters relating to each of the dispatches, where evaluating further includes associating a first plan with one or more of the dispatches to transform the command stream into a transformed command stream. The method may further include associating, based on the first plan, a second plan to the one or more of the dispatches, where the second plan represents the transformed command stream. The method may further include executing the second plan, where execution of the second plan includes processing the transformed command stream in lieu of the command stream.

    Abstract translation: 描述了一种机制，用于促进图形处理命令的动态运行时转换，以改善计算设备上的图形性能。 如本文所述的实施例的方法包括检测与应用相关联的命令流，其中命令流包括分派。 该方法还可以包括评估与每个调度有关的处理参数，其中评估进一步包括将第一计划与一个或多个调度相关联，以将命令流变换成变换的命令流。 该方法可以进一步包括：基于第一计划，将第二计划与一个或多个调度相关联，其中第二计划表示变换的命令流。 该方法还可以包括执行第二计划，其中第二计划的执行包括处理变换的命令流来代替命令流。

    VIRTUAL ADDRESS ACCESS TO GPU SURFACE AND SAMPLER STATES
    24.
    发明公开
    VIRTUAL ADDRESS ACCESS TO GPU SURFACE AND SAMPLER STATES 审中-公开

    公开(公告)号：US20240231621A9

    公开(公告)日：2024-07-11

    申请号：US17971290

    申请日：2022-10-21

    Applicant: Intel Corporation

    Inventor： Joydeep Ray ,  Michael Apodaca ,  Yoav Harel ,  Guei-Yuan Lueh ,  John A. Wiegert

    IPC: G06F3/06 ,  G06T1/60

    CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0679 ,  G06T1/60

    Abstract: Embodiments described herein provide a technique to enable access to entries in a surface state or sampler state using 64-bit virtual addresses. One embodiment provides a graphics core that includes memory access circuitry configured to facilitate access to the memory by functional units of the graphics core. The memory access circuitry is configured to receive a message to access an entry in a surface state or a sampler state associated with a parallel processing operation. The message specifies a base address for a surface state entry or sampler state entry. The circuitry can add the base address and the offset to determine a 64-bit virtual address for the entry in the surface state entry or the sampler state and submit a memory access request to the memory to access the entry of the surface state or sampler state.

    Mutli-frame renderer
    27.
    发明授权
    Mutli-frame renderer 有权

    公开(公告)号：US11636567B2

    公开(公告)日：2023-04-25

    申请号：US17486330

    申请日：2021-09-27

    Applicant: Intel Corporation

    Inventor： Abhishek Venkatesh ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Prasoonkumar Surti

    IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38 ,  G06T15/00

    Abstract: An embodiment of a graphics command coordinator apparatus may include a commonality identifier to identify a commonality between a first graphics command corresponding to a first frame and a second graphics command corresponding to a second frame, a commonality analyzer communicatively coupled to the commonality identifier to determine if the first graphics command and the second graphics command can be processed together based on the commonality identified by the commonality identifier, and a commonality indicator communicatively coupled to the commonality analyzer to provide an indication that the first graphics command and the second graphics command are to be processed together. Other embodiments are disclosed and claimed.

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