公开(公告)号：US20200027856A1

公开(公告)日：2020-01-23

申请号：US16586820

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Rahul JAIN ,  Ji Yong PARK ,  Kyu Oh LEE

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

公开(公告)号：US20190355675A1

公开(公告)日：2019-11-21

申请号：US15982652

申请日：2018-05-17

Applicant: Intel Corporation

Inventor： Kyu-Oh LEE ,  Sai VADLAMANI ,  Rahul JAIN ,  Junnan ZHAO ,  Ji Yong PARK ,  Cheng XU ,  Seo Young KIM

IPC: H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01F1/12 ,  H01F41/14

Abstract: Techniques for fabricating a semiconductor package having magnetic materials embedded therein are described. For one technique, fabrication of package includes: forming a pad and a conductive line on a build-up layer; forming a raised pad structure on the build-up layer, the raised pad comprising a pillar structure on the pad; encapsulating the conductive line and the raised pad structure in a magnetic film comprising one or more magnetic fillers; planarizing a top surface of the magnetic film until top surfaces of the raised pad structure and the magnetic film are co-planar; depositing a primer layer on the top surfaces; removing one or more portions of the primer layer above the raised pad structure to create an opening; and forming a via in the opening on the raised pad structure. The primer layer may comprise one or more of a build-up layer, a photoimageable dielectric layer, and a metal mask.

公开(公告)号：US20190244922A1

公开(公告)日：2019-08-08

申请号：US16386195

申请日：2019-04-16

Applicant: Intel Corporation

Inventor： Rahul JAIN ,  Kyu Oh LEE ,  Amanda E. SCHUCKMAN ,  Steve S. CHO

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L23/498 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/11462 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13155 ,  H01L2224/16157 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83951 ,  H01L2924/15311 ,  H05K1/00 ,  H01L2924/00

Abstract: Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes nickel and tin, wherein the nickel aids in mitigating an absorption of seed layer copper. In another embodiment, the microbump has a mass fraction of tin, or a mass fraction of nickel, that is different in various regions along a height of the microbump.