公开(公告)号：US20220328431A1

公开(公告)日：2022-10-13

申请号：US17852003

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Cheng XU ,  Kyu-Oh LEE ,  Junnan ZHAO ,  Rahul JAIN ,  Ji Yong PARK ,  Sai VADLAMANI ,  Seo Young KIM

IPC: H01L23/64 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.

公开(公告)号：US20220359115A1

公开(公告)日：2022-11-10

申请号：US17873509

申请日：2022-07-26

Applicant: Intel Corporation

Inventor： Kyu-Oh LEE ,  Rahul JAIN ,  Sai VADLAMANI ,  Cheng XU ,  Ji Yong PARK ,  Junnan ZHAO ,  Seo Young KIM

IPC: H01F27/32 ,  H01L23/498 ,  H01F41/04 ,  H01L21/48 ,  H01F27/28

Abstract: Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.

公开(公告)号：US20220199503A1

公开(公告)日：2022-06-23

申请号：US17129846

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Manish DUBEY ,  Guruprasad ARAKERE ,  Deepak KULKARNI ,  Sairam AGRAHARAM ,  Wei-Lun K. JEN ,  Numair AHMED ,  Kousik GANESAN ,  Amol D. JADHAV ,  Kyu-Oh LEE

IPC: H01L23/498 ,  H01L21/48

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate with a die side and a land side. In an embodiment, a pad is on the land side. In an embodiment, a dielectric layer covers sidewalls of the pad, and a surface finish is over an exposed surface of the pad.

公开(公告)号：US20190304933A1

公开(公告)日：2019-10-03

申请号：US15938114

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Cheng XU ,  Kyu-Oh LEE ,  Junnan ZHAO ,  Rahul JAIN ,  Ji Yong PARK ,  Sai VADLAMANI ,  Seo Young KIM

IPC: H01L23/64 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.

公开(公告)号：US20220367104A1

公开(公告)日：2022-11-17

申请号：US17873518

申请日：2022-07-26

Applicant: Intel Corporation

Inventor： Cheng XU ,  Kyu-Oh LEE ,  Junnan ZHAO ,  Rahul JAIN ,  Ji Yong PARK ,  Sai VADLAMANI ,  Seo Young KIM

IPC: H01F27/28 ,  H01F27/02 ,  H01F27/24

Abstract: Embodiments include an inductor that comprises an inductor trace and a magnetic body surrounding the inductor trace. In an embodiment, the magnetic body comprises a first step surface and a second step surface. Additional embodiments include an inductor that includes a barrier layer. In an embodiment, an inductor trace is formed over a first surface of the barrier layer. Embodiments include a first magnetic body over the inductor trace and the first surface of the barrier layer, and a second magnetic body over a second surface of the barrier layer opposite the first surface. In an embodiment, a width of the second magnetic body is greater than a width of the first magnetic body.

公开(公告)号：US20220165695A1

公开(公告)日：2022-05-26

申请号：US17104919

申请日：2020-11-25

Applicant: Intel Corporation

Inventor： Numair AHMED ,  Kyu-Oh LEE ,  Brandon C. MARIN ,  Gang DUAN

IPC: H01L23/00 ,  H01L23/498

Abstract: Embodiments disclosed herein include electronic packages with fin pitch first level interconnects. In an embodiment, the electronic package comprises a die and a package substrate attached to the die by a plurality of first level interconnects (FLIs). In an embodiment, individual ones of the plurality of FLIs comprise, a first pad on the package substrate, a solder on the first pad, a second pad on the die, and a bump on the second pad. In an embodiment, the bump comprises a porous nanostructure, and the solder at least partially fills the porous nanostructure.

公开(公告)号：US20200294938A1

公开(公告)日：2020-09-17

申请号：US16353164

申请日：2019-03-14

Applicant: Intel Corporation

Inventor： Rahul JAIN ,  Kyu-Oh LEE ,  Islam A. SALAMA ,  Amruthavalli P. ALUR ,  Wei-Lun K. JEN ,  Yongki MIN ,  Sheng C. LI

IPC: H01L23/64 ,  H01L23/498 ,  H01L49/02 ,  H01L23/538

Abstract: Embodiments include semiconductor packages. A semiconductor package includes a plurality of build-up layers and a plurality of conductive layers in the build-up layers. The conductive layers include a first conductive layer and a second conductive layer. The first conductive layer is over the second conductive layer and build-up layers, where a first via couples the first and second conductive layers. The semiconductor package also includes a thin film capacitor (TFC) in the build-up layers, where a second via couples the TFC to the first conductive layer, and the second via has a thickness less than a thickness of the first via. The first conductive layer may be first level interconnects. The build-up layers may be dielectrics. The TFC may include a first electrode, a second electrode, and a dielectric. The first electrode may be over the second electrode, and the dielectric may be between the first and second electrodes.

公开(公告)号：US20190355675A1

公开(公告)日：2019-11-21

申请号：US15982652

申请日：2018-05-17

Applicant: Intel Corporation

Inventor： Kyu-Oh LEE ,  Sai VADLAMANI ,  Rahul JAIN ,  Junnan ZHAO ,  Ji Yong PARK ,  Cheng XU ,  Seo Young KIM

IPC: H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01F1/12 ,  H01F41/14

Abstract: Techniques for fabricating a semiconductor package having magnetic materials embedded therein are described. For one technique, fabrication of package includes: forming a pad and a conductive line on a build-up layer; forming a raised pad structure on the build-up layer, the raised pad comprising a pillar structure on the pad; encapsulating the conductive line and the raised pad structure in a magnetic film comprising one or more magnetic fillers; planarizing a top surface of the magnetic film until top surfaces of the raised pad structure and the magnetic film are co-planar; depositing a primer layer on the top surfaces; removing one or more portions of the primer layer above the raised pad structure to create an opening; and forming a via in the opening on the raised pad structure. The primer layer may comprise one or more of a build-up layer, a photoimageable dielectric layer, and a metal mask.

公开(公告)号：US20190081002A1

公开(公告)日：2019-03-14

申请号：US16184726

申请日：2018-11-08

Applicant: Intel Corporation

Inventor： Kyu-Oh LEE

IPC: H01L23/538

Abstract: Semiconductor packages with embedded bridge interconnects, and related assemblies and methods, are disclosed herein. In some embodiments, a semiconductor package may have a first side and a second side, and may include a bridge interconnect, embedded in a build-up material, having a first side with a plurality of conductive pads. The semiconductor package may also include a via having a first end that is narrower than a second end. The bridge interconnect and via may be arranged so that the first side of the semiconductor package is closer to the first side of the bridge interconnect than to the second side of the bridge interconnect, and so that the first side of the semiconductor package is closer to the first end of the via than to the second end of the via. Other embodiments may be disclosed and/or claimed.