公开(公告)号：US09461014B2

公开(公告)日：2016-10-04

申请号：US14686177

申请日：2015-04-14

Applicant: Intel Corporation

Inventor： Sriram Srinivasan ,  Ram S. Viswanath ,  Paul R. Start ,  Rajen S. Sidhu ,  Rajasekaran Swaminathan

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/498 ,  H01L23/367 ,  H01L23/42

CPC classification number: H01L24/81 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81801 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/20105 ,  H01L2924/2064 ,  H01L2924/20643 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include attaching a device to a patch substrate, wherein the assembled device and patch substrate comprise a warpage, attaching the assembled device and patch substrate to an interposer to form a package structure, and then reflowing the package structure at a temperature below about 200 degrees Celsius to form a substantially flat package structure.

公开(公告)号：US09391013B2

公开(公告)日：2016-07-12

申请号：US14813014

申请日：2015-07-29

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Ram S. Viswanath ,  Sriram Srinivasan ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Sairam Agraharam

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/13 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/00

Abstract: 3D integrated circuit packages with window interposers and methods to form such semiconductor packages are described. For example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer having a window is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in the window of the interposer and interconnected to the top semiconductor die. In another example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in a same plane as the interposer and interconnected to the top semiconductor die.

公开(公告)号：US20150221609A1

公开(公告)日：2015-08-06

申请号：US14686177

申请日：2015-04-14

Applicant: Intel Corporation

Inventor： Sriram Srinivasan ,  Ram S. Viswanath ,  Paul R. Start ,  Rajen S. Sidhu ,  Rajasekaran Swaminathan

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81801 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/20105 ,  H01L2924/2064 ,  H01L2924/20643 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include attaching a device to a patch substrate, wherein the assembled device and patch substrate comprise a warpage, attaching the assembled device and patch substrate to an interposer to form a package structure, and then reflowing the package structure at a temperature below about 200 degrees Celsius to form a substantially flat package structure.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法和结构可以包括将装置附接到贴片基板，其中组装的装置和贴片基板包括翘曲，将组装的装置和贴片基板附接到插入件以形成封装结构，然后在温度下回流封装结构 低于大约200摄氏度以形成基本平坦的包装结构。

公开(公告)号：US09064971B2

公开(公告)日：2015-06-23

申请号：US13721329

申请日：2012-12-20

Applicant: Intel Corporation

Inventor： Sriram Srinivasan ,  Ram S. Viswanath ,  Paul R. Start ,  Rajen S. Sidhu ,  Rajasekaran Swaminathan

IPC: H01L29/40 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81801 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/20105 ,  H01L2924/2064 ,  H01L2924/20643 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include attaching a device to a patch substrate, wherein the assembled device and patch substrate comprise a warpage, attaching the assembled device and patch substrate to an interposer to form a package structure, and then reflowing the package structure at a temperature below about 200 degrees Celsius to form a substantially flat package structure.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法和结构可以包括将装置附接到贴片基板，其中组装的装置和贴片基板包括翘曲，将组装的装置和贴片基板附接到插入件以形成封装结构，然后在温度下回流封装结构 低于大约200摄氏度以形成基本平坦的包装结构。