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21.发明申请公开(公告)号：US20180091293A1
公开(公告)日：2018-03-29
申请号：US15277856
申请日：2016-09-27
Applicant: Intel Corporation
Inventor： Vikram B. Suresh , Sanu K. Mathew , Sudhir K. Satpathy
IPC: H04L9/00 , H03K19/003
CPC classification number: H04L9/002 , H03K19/003
Abstract: Embodiments include apparatuses, methods, and systems for a physically unclonable function (PUF) circuit. The PUF circuit may include an array of PUF cells to generate respective response bits of an authentication code in response to a challenge bit string. The PUF cells may include a pair of cross-coupled inverters, the individual inverters including independently selectable pull-down or pull-up legs. One of the pull-up or pull-down legs of each inverter may be selectively activated based on the challenge bit string. The PUF cells may further include first and second configurable clock delay circuits to pass respective clock signals to pre-charge transistors of the PUF cell. A dark bit masking circuit may generate a soft dark bit mask for the PUF circuit. Other embodiments may be described and claimed.
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公开(公告)号：US20170134163A1
公开(公告)日：2017-05-11
申请号：US14933011
申请日：2015-11-05
Applicant: Intel Corporation
Inventor： Vikram B. Suresh , Sudhir K. Satpathy , Sanu K. Mathew
CPC classification number: H04L9/0643 , G06F9/3895 , H04L9/3239 , H04L2209/12 , H04L2209/125
Abstract: In an embodiment, a processor includes a hardware accelerator to receive a message to be processed using the cryptographic hash algorithm; store a plurality of digest words in a plurality of digest registers; perform a plurality of rounds of the cryptographic hash algorithm, where the plurality of rounds is divided into first and second sets of rounds; in each cycle of each round in the first set, use W bits from the first digest register for a first function and use N bits from the second digest register for a second function; in each cycle of each round in the second set, use W bits from the second digest register for the first function and use N bits from the first digest register for the second function. Other embodiments are described and claimed.
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公开(公告)号：US11595055B2
公开(公告)日：2023-02-28
申请号：US17586598
申请日：2022-01-27
Applicant: Intel Corporation
Inventor： Vinodh Gopal , James D. Guilford , Sudhir K. Satpathy , Sanu K. Mathew
Abstract: Methods and apparatus to parallelize data decompression are disclosed. An example method selecting initial starting positions in a compressed data bitstream; adjusting a first one of the initial starting positions to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream, the decoding including traversing the bitstream from the training position as though first data located at the training position is a valid token; outputting first decoded data generated by decoding a first segment of the bitstream starting from the first adjusted starting position; and merging the first decoded data with second decoded data generated by decoding a second segment of the bitstream, the decoding of the second segment starting from a second position in the bitstream and being performed in parallel with the decoding of the first segment, and the second segment preceding the first segment in the bitstream.
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公开(公告)号：US10763894B2
公开(公告)日：2020-09-01
申请号：US16402845
申请日：2019-05-03
Applicant: Intel Corporation
Inventor： Vinodh Gopal , James D. Guilford , Sudhir K. Satpathy , Sanu K. Mathew
Abstract: Methods and apparatus to parallelize data decompression are disclosed. An example method selecting initial starting positions in a compressed data bitstream; adjusting a first one of the initial starting positions to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream, the decoding including traversing the bitstream from the training position as though first data located at the training position is a valid token; outputting first decoded data generated by decoding a first segment of the bitstream starting from the first adjusted starting position; and merging the first decoded data with second decoded data generated by decoding a second segment of the bitstream, the decoding of the second segment starting from a second position in the bitstream and being performed in parallel with the decoding of the first segment, and the second segment preceding the first segment in the bitstream.
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公开(公告)号：US20200099958A1
公开(公告)日：2020-03-26
申请号：US16137985
申请日：2018-09-21
Applicant: Intel Corporation
Inventor： Sudhir K. Satpathy , Vinodh Gopal , James D. Guilford , Sanu K. Mathew , Vikram B. Suresh
Abstract: A processing device includes compression circuitry to encode an input stream with an encoding that translates multiple symbols of fixed length into multiple codes of variable length between one and a maximum length, to generate a compressed stream. The compression circuitry is to: determine at least a first symbol of the multiple symbols having a first code that exceeds the maximum length; identify a short code of the multiple codes that is to be lengthened to provide an increased encoding capacity for the at least the first symbol; generate multiple code-length converted values including to increase the length of the short code to the maximum length and decrease, to the maximum length, a length of the first code of the at least the first symbol; and generate, with use of the set of code-length converted values, the compressed stream at the output terminal.
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Patent Agency Ranking
公开(公告)号：US20180341722A1
公开(公告)日：2018-11-29
申请号：US15604793
申请日：2017-05-25
Applicant: Intel Corporation
Inventor： Sudhir K. Satpathy , Vikram B. Suresh , Sanu K. Mathew , Vinodh Gopal
IPC: G06F17/30 , G06F12/1018
Abstract: In one embodiment, an apparatus comprises a decompression engine to determine a plurality of tokens used to encode a block of data; populate a lookup table with at least two of the tokens in order of increasing token length; disable a first portion of the lookup table and enable a second portion of the lookup table based on a value of a payload of the block of data; and search for a match between a token and the payload in the second portion of the lookup table.
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公开(公告)号：US10135463B1
公开(公告)日：2018-11-20
申请号：US15721343
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Sudhir K. Satpathy , James D. Guilford , Vinodh Gopal , Kirk S. Yap
Abstract: In one embodiment, an apparatus comprises a memory; and a compression engine comprising circuitry, the compression engine to assign weights to a plurality of first symbols of a data set, a weight representing a frequency of a corresponding first symbol in the data set; perform a partial sort of the first symbols based on the assigned weights; generate at least a portion of a Huffman tree based on the partial sort; and create a plurality of Huffman codes for the plurality of first symbols based on the Huffman tree.
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公开(公告)号：US10083034B1
公开(公告)日：2018-09-25
申请号：US15713526
申请日：2017-09-22
Applicant: Intel Corporation
Inventor： Sudhir K. Satpathy , Vinodh Gopal
CPC classification number: G06F9/3016 , G06F9/3004 , G06F9/30149 , H03M7/00 , H03M7/4037 , H03M7/6005 , H03M7/6023 , H04L69/04
Abstract: In one embodiment, an apparatus comprises a memory, a processor and a prefix decoder engine to access a plurality of code lengths of a header associated with a compressed data block; determine a number of instances of each code length of at least some of the plurality of code lengths; and operate a plurality of decode streams in parallel, a first decode stream of the plurality of decode streams to iterate through a first portion of the plurality of code lengths and determine codes corresponding to the first portion of the plurality of code lengths, a second decode stream of the plurality of decode streams to iterate through a second portion of the plurality of code lengths and determine codes corresponding to the second portion of the plurality of code lengths.
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公开(公告)号：US10042644B2
公开(公告)日：2018-08-07
申请号：US15371091
申请日：2016-12-06
Applicant: Intel Corporation
Inventor： Sudhir K. Satpathy , Sanu K. Mathew , Vinodh Gopal , James D. Guilford
Abstract: An apparatus and method for performing parallel decoding of prefix codes such as Huffman codes. For example, one embodiment of an apparatus comprises: a first decompression module to perform a non-speculative decompression of a first portion of a prefix code payload comprising a first plurality of symbols; and a second decompression module to perform speculative decompression of a second portion of the prefix code payload comprising a second plurality of symbols concurrently with the non-speculative decompression performed by the first compression module.
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公开(公告)号：US20180097615A1
公开(公告)日：2018-04-05
申请号：US15282232
申请日：2016-09-30
Applicant: Intel Corporation
Inventor： Vikram B. Suresh , Sanu K. Mathew , Sudhir K. Satpathy
CPC classification number: H04L9/0643 , H03K19/20
Abstract: Described is an apparatus comprising precharge paths including first clocked transistors having gates coupled to a clock signal path, first terminals coupled to a first power rail, and second terminals coupled to one or more first junction nodes. The precharge paths lack a keeper circuitry, have a configurable keeper circuitry, and/or have cross-coupled keeper circuitry to eliminate/reduce keeper contention during domino logic evaluation. The apparatus may comprise second clocked transistors having gates coupled to the clock signal path, first terminals coupled to one or more second junction nodes, and second terminals coupled to a second power rail. The apparatus may comprise sets of evaluation transistors having conducting channels coupled in series, coupled to the one or more first junction nodes, and coupled to one of the one or more second junction nodes. A NAND or inverter circuitry with inputs is coupled to the one or more first junction nodes.
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