公开(公告)号：US20240329333A1

公开(公告)日：2024-10-03

申请号：US18129690

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Robert May ,  Bai Nie ,  Changhua Liu ,  Hiroki Tanaka ,  Kristof Darmawikarta ,  Lilia May ,  Shriya Seshadri ,  Srinivas Pietambaram ,  Tarek Ibrahim

IPC: G02B6/42 ,  G02B6/13 ,  H01L25/065 ,  H01L25/16

CPC classification number: G02B6/4202 ,  G02B6/13 ,  H01L25/0655 ,  H01L25/167 ,  G02B2006/12038

Abstract: Multi-die packages including both photonic and electric integrated circuit (IC) die interconnected to each other through a routing structure built-up on a glass substrate. A glass preform comprising an optical waveguide may also be attached to the routing structure. A plurality of electrical IC (EIC) die may be arrayed over the routing structure along with a plurality of photonic IC (PIC). Each PIC may be coupled to an optical waveguide within the glass preform. Conductive vias may extend through the glass substrate and be further coupled with a host substrate. The host substrate may comprise glass and an optical waveguide embedded within the glass. A vertical coupler may be attached to the host substrate to optically couple the host substrate to the optical waveguide within the glass preform of the multi-die package. Many of the multi-die packages may be arrayed over a routing structure on the host substrate.

公开(公告)号：US20240111090A1

公开(公告)日：2024-04-04

申请号：US17957341

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Robert A. May ,  Tarek Ibrahim ,  Shriya Seshadri ,  Kristof Darmawikarta ,  Hiroki Tanaka ,  Changhua Liu ,  Bai Nie ,  Lilia May ,  Srinivas Pietambaram ,  Zhichao Zhang ,  Duye Ye ,  Yosuke Kanaoka ,  Robin McRee

IPC: G02B6/12 ,  G02B6/13

CPC classification number: G02B6/12004 ,  G02B6/13 ,  G02B2006/12171

Abstract: A device comprises a substrate and an IC die, which may be a photonic IC. The substrate comprises a first surface, a second surface opposite the first surface, an optical waveguide integral with the substrate, and a hole extending from the first surface to the second surface. The hole comprises a first sidewall. The optical waveguide is between the first surface and the second surface, parallel to the first surface, and comprises a first end which extends to the first sidewall. The IC die is within the hole and comprises a second sidewall and an optical port at the second sidewall. The second sidewall is proximate to the first sidewall and the first end of the optical waveguide is proximate to and aligned with the optical port. The substrate may include a recess to receive another device comprising a socket.

公开(公告)号：US11798887B2

公开(公告)日：2023-10-24

申请号：US17492476

申请日：2021-10-01

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Tarek Ibrahim ,  Kristof Darmawikarta ,  Rahul N. Manepalli ,  Debendra Mallik ,  Robert L. Sankman

IPC: H01L23/538 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5383 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/09 ,  H01L25/0652

Abstract: A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.

公开(公告)号：US11622448B2

公开(公告)日：2023-04-04

申请号：US16505403

申请日：2019-07-08

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Tarek Ibrahim ,  Srinivas Pietambaram ,  Andrew J. Brown ,  Gang Duan ,  Jeremy Ecton ,  Sheng C. Li

IPC: H05K1/11 ,  H05K1/16 ,  H01L23/00 ,  H01F27/40 ,  H05K3/40 ,  H05K3/28

Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a first encapsulation layer over a substrate, and a second encapsulation layer below the substrate. The package substrate also includes a first interconnect and a second interconnect vertically in the first encapsulation layer, the second encapsulation layer, and the substrate. The first interconnect includes a first plated-through-hole (PTH) core, a first via, and a second via, and the second interconnect includes a second PTH core, a third via, and a fourth via. The package substrate further includes a magnetic portion that vertically surrounds the first interconnect. The first PTH core has a top surface directly coupled to the first via, and a bottom surface directly coupled to the second via. The second PTH core has a top surface directly coupled to the third via, and a bottom surface directly coupled to the fourth via.

公开(公告)号：US11164818B2

公开(公告)日：2021-11-02

申请号：US16363698

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Tarek Ibrahim ,  Kristof Darmawikarta ,  Rahul N. Manepalli ,  Debendra Mallik ,  Robert L. Sankman

IPC: H01L23/538 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.

公开(公告)号：US20200312767A1

公开(公告)日：2020-10-01

申请号：US16363698

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Tarek Ibrahim ,  Kristof Darmawikarta ,  Rahul N. Manepalli ,  Debendra Mallik ,  Robert L. Sankman

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L23/48

Abstract: A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.