公开(公告)号：US20250112165A1

公开(公告)日：2025-04-03

申请号：US18478250

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Brandon Marin ,  Hiroki Tanaka ,  Robert May ,  Srinivas Pietambaram ,  Gang Duan ,  Suddhasattwa Nad ,  Numair Ahmed ,  Jeremy Ecton ,  Benjamin Taylor Duong ,  Bai Nie ,  Haobo Chen ,  Xiao Liu ,  Bohan Shan ,  Shruti Sharma ,  Mollie Stewart

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00

Abstract: Anisotropic conductive connections for interconnect bridges and related methods are disclosed herein. An example a package substrate for an integrated circuit package, the package substrate comprising a first pad disposed at a first end of an interconnect within the package substrate, the first pad disposed in a cavity in the package substrate, an interconnect bridge disposed in the cavity, the interconnect bridge including a second pad, and a third pad, and a layer disposed between the first pad and the second pad, the layer having a first conductivity between the first pad and the second pad, the layer having a second conductivity between the second pad and the third pad, the first conductivity greater than the second conductivity.

公开(公告)号：US20250112138A1

公开(公告)日：2025-04-03

申请号：US18374592

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Gang Duan ,  Sameer Paital ,  Zhixin Xie ,  Rahul Manepalli ,  Jieying Kong

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/15

Abstract: Microelectronic integrated circuit package structures include an apparatus having a substrate comprising a layer of glass, the substrate comprising one or more through glass vias (TGVs) extending through the layer of glass. Individual TGVs comprise a TGV sidewall, an organic dielectric layer on the TGV sidewall and a conductive layer on the organic dielectric layer.

公开(公告)号：US20250112100A1

公开(公告)日：2025-04-03

申请号：US18375209

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Robert May ,  Hiroki Tanaka ,  Tarek Ibrahim ,  Lilia May ,  Jason Gamba ,  Benjamin Duong ,  Brandon Marin ,  Srinivas Pietambaram ,  Gang Duan ,  Suddhasattwa Nad ,  Jeremy Ecton

IPC: H01L23/29 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

Abstract: An IC die package includes first and second IC die on a first surface of a glass layer, a bridge under the first and second IC die within an opening in the glass layer, and first and second package conductive features on a second surface of the glass layer opposite the first side. First interconnects comprising solder couple the bridge with the first and second IC die. Second interconnects excluding solder couple the first and second IC die with vias extending through the glass layer to the first package conductive features. Third interconnects excluding solder couple the bridge with the second package conductive features. The bridge couples the first and second IC die with each other, and the first and second IC die with the second package conductive features. A pitch of conductive features in the first interconnects is less than a pitch of conductive features in the second interconnects.

公开(公告)号：US20250105209A1

公开(公告)日：2025-03-27

申请号：US18475373

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Gang Duan ,  Yosuke Kanaoka ,  Minglu Liu ,  Srinivas V. Pietambaram ,  Brandon C. Marin ,  Bohan Shan ,  Haobo Chen ,  Jeremy Ecton ,  Benjamin T. Duong ,  Suddhasattwa Nad

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/42 ,  H01L23/538 ,  H10B80/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer having first dies in a first insulating material; a second layer on the first layer, the second layer including second dies having a first thickness and third dies having a second thickness different than the first thickness, the second dies and the third dies in a second insulating material, wherein the second dies and third dies have a first surface and an opposing second surface, and wherein the first surfaces of the second and third dies have a combined surface area between 3,000 square millimeters (mm2) and 9,000 mm2; and a redistribution layer (RDL) between the first layer and the second layer, the RDL including conductive pathways, wherein the first dies are electrically coupled to the second dies and the third dies by the conductive pathways and by interconnects.

公开(公告)号：US20250096143A1

公开(公告)日：2025-03-20

申请号：US18470668

申请日：2023-09-20

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Tarek A. Ibrahim ,  Srinivas V. Pietambaram ,  Gang Duan

IPC: H01L23/538 ,  H01L21/48

Abstract: A microelectronic assembly includes a bridge die embedded in a substrate. The substrate includes a doped dielectric material in a layer or region directly below the bridge die, and in a layer near an upper face of the bridge die. A cavity is formed in the upper layer of the doped dielectric material for embedding the bridge die, exposing the lower layer of the doped dielectric material. After cavity formation, a selective metallization of the lower and upper layers of the doped dielectric material is performed, providing well-aligned metal layers in the region of the bridge die and the region around the bridge die.

公开(公告)号：US20250006665A1

公开(公告)日：2025-01-02

申请号：US18883825

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Gang Duan ,  Minglu Liu ,  Srinivas Venkata Ramanuja Pietambaram

IPC: H01L23/64 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/498 ,  H01L23/535 ,  H01L25/11 ,  H01L25/18 ,  H01L29/66

Abstract: Systems, apparatus, articles of manufacture, and methods for stacks of glass layers including deep trench capacitors are disclosed. An example substrate for an integrated circuit package disclosed herein includes a first glass layer, a second glass layer coupled to the first glass layer, and a deep trench capacitor embedded in the first core.

公开(公告)号：US20250006611A1

公开(公告)日：2025-01-02

申请号：US18883786

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Minglu Liu

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/64 ,  H01L25/065

Abstract: Systems, apparatus, articles of manufacture, and methods for power delivery through package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example integrated circuit (IC) package includes: a package core including a first glass sheet and a second glass sheet distinct from the first glass sheet, the first glass sheet having a different coefficient of thermal expansion (CTE) from the second glass sheet; a first redistribution layer on a first side of the package core; a second redistribution layer on a second side of the package core, the second side opposite the first side; and an interconnect extending through the package core, the interconnect including a magnetic material.

公开(公告)号：US20250006610A1

公开(公告)日：2025-01-02

申请号：US18883781

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Minglu Liu

IPC: H01L23/498 ,  H01L23/15 ,  H01L25/065

Abstract: Systems, apparatus, articles of manufacture, and methods for power delivery through package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example substrate for an integrated circuit package includes: a first glass layer having a first coefficient of thermal expansion (CTE); a second glass layer having a second CTE, the second CTE different from the first CTE; and a magnetic material lining a first wall of a first opening in the first glass layer and lining a second wall of a second opening in the second glass layer.

公开(公告)号：US20240355749A1

公开(公告)日：2024-10-24

申请号：US18756580

申请日：2024-06-27

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Gang Duan ,  Jefferson Coker Kaplan ,  Brandon Christian Marin ,  Srinivas Venkata Ramanuja Pietambaram

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/15 ,  H01L25/16

CPC classification number: H01L23/5385 ,  H01L23/15 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/162 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Disaggregated package substrates with glass cores are disclosed. An example package substrate includes a glass core having a first side and a second side opposite the first side. The example package substrate further includes a first block of redistribution layers on the first side of the glass core. The example package substrate also includes a second block of redistribution layers on the first side of the glass core. The first block is distinct from the second block.

公开(公告)号：US20240332134A1

公开(公告)日：2024-10-03

申请号：US18193182

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Liang He ,  Jung Kyu Han ,  Gang Duan

IPC: H01L23/495 ,  H01L21/768 ,  H01L23/00 ,  H01L23/15 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/49513 ,  H01L21/76898 ,  H01L23/15 ,  H01L23/5283 ,  H01L23/53228 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/05147 ,  H01L2224/06131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131

Abstract: Methods and apparatus to mitigate electromigration are disclosed. A disclosed example integrated circuit (IC) package includes a dielectric substrate, a contact pad at least partially extending though or positioned on the dielectric substrate, the contact pad including copper, and a metal interconnect coupled to the contact pad, the interconnect including indium.