中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

34 records (took 0.02 seconds)

    Cooler for semiconductor devices
    23.
    发明授权
    Cooler for semiconductor devices 有权

    公开(公告)号：US10121726B2

    公开(公告)日：2018-11-06

    申请号：US14839510

    申请日：2015-08-28

    Applicant: Intel IP Corporation

    Inventor： Sven Albers ,  Klaus Reingruber ,  Andreas Wolter ,  Georg Seidemann ,  Christian Geissler ,  Alexandra Atzesdorfer ,  Sonja Koller

    IPC: H01L23/373 ,  H01L23/36 ,  G06F1/20 ,  H01L23/427

    Abstract: Embodiments of the present disclosure relate to a cooler for semiconductor devices. The semiconductor device may be electrically coupleable to a power source. The device may generate heat when the power source supplies power to the device during use of the device. The cooler may be coupled to one or more surfaces of the device. The cooler may include a hydrophilic material to adsorb water from ambient air. During operation of the device, the cooler may cool the device by conduction of heat away from the device to the cooler. The cooler may include water that is evaporated during use of the device to increase cooling capacity of the cooler. The cooler may be recharged with water from humidity in air when the device is not operated or operated at a lower power level. Other embodiments may be described and/or claimed.

    Electronic package with coil formed on core
    24.
    发明授权
    Electronic package with coil formed on core 有权

    公开(公告)号：US09865387B2

    公开(公告)日：2018-01-09

    申请号：US14956859

    申请日：2015-12-02

    Applicant: Intel IP Corporation

    Inventor： Sven Albers ,  Klaus Reingruber ,  Andreas Wolter

    IPC: H01F5/00 ,  H01F27/06 ,  H01F27/28 ,  H01F27/24

    CPC classification number: H01F27/2804 ,  H01F27/06 ,  H01F27/24 ,  H01F2027/065 ,  H01F2027/2809

    Abstract: An electronic package that includes a substrate; a first electronic component mounted on one side of the substrate; a second electronic component mounted on an opposing side of the substrate; a core mounted to the substrate, wherein the core extends through the substrate; a first wire electrically attached to at least one of the first electronic component and the substrate, wherein the first wire is wrapped around the core to form a first coil on the one side of the substrate; and a second wire electrically attached to at least one of the second electronic component and the substrate, wherein the second wire is wrapped around the core to form a second coil on the opposing side of the substrate.

    REDISTRIBUTION LAYER LINES
    26.
    发明申请
    REDISTRIBUTION LAYER LINES 有权

    公开(公告)号：US20170243815A1

    公开(公告)日：2017-08-24

    申请号：US15052505

    申请日：2016-02-24

    Applicant: Intel IP Corporation

    Inventor： Klaus Reingruber ,  Sven Albers ,  Christian Geissler

    IPC: H01L23/498 ,  H01L21/48

    CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L24/19 ,  H01L2224/04105

    Abstract: Embodiments herein may relate to a package with a dielectric layer having a first face and a second face opposite the first face. A conductive line of a patterned metal redistribution layer (RDL) may be coupled with the second face of the dielectric layer. The line may include a first portion with a first width and a second portion directly coupled to the first portion, the second portion having a second width. The first portion may extend beyond a plane of the second face of the dielectric layer, and the second portion may be positioned between the first face and the second face of the dielectric layer. Other embodiments may be described and/or claimed.

    Interposer with conductive routing exposed on sidewalls
    28.
    发明授权
    Interposer with conductive routing exposed on sidewalls 有权

    公开(公告)号：US10651102B2

    公开(公告)日：2020-05-12

    申请号：US15778410

    申请日：2015-12-18

    Applicant: Intel IP Corporation

    Inventor： Klaus Reingruber ,  Christian Geissler ,  Georg Seidemann ,  Sonja Koller

    IPC: H01L23/48 ,  H01L23/13 ,  H01L23/12 ,  H01L23/498 ,  H05K3/40 ,  H05K1/18

    Abstract: An electronic assembly that includes an electronic component; and an interposer that includes a body having upper and lower surfaces and side walls extending between the upper and lower surfaces, the interposer further including conductive routings that are exposed on at least one of the side walls, wherein the electronic component is connected directly to the interposer. The conductive routings are exposed on each side wall and on the upper and lower surfaces. The electronic assembly may further includes a substrate having a cavity such that the interposer is within the cavity, wherein the cavity includes sidewalls and substrate includes conductive traces that are exposed from the sidewalls of the cavity, wherein the conductive traces that are exposed from the sidewalls of the cavity are electrically connected directly to the conductive routings that are exposed on at least one of the side walls of the interposer.

    Advanced node cost reduction by ESD interposer
    29.
    发明授权
    Advanced node cost reduction by ESD interposer 有权

    公开(公告)号：US10446541B2

    公开(公告)日：2019-10-15

    申请号：US15743996

    申请日：2015-09-14

    Applicant: Intel IP Corporation

    Inventor： Georg Seidemann ,  Christian Geissler ,  Klaus Reingruber

    IPC: H01L23/48 ,  H01L27/02 ,  H01L23/60 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L49/02 ,  H01L25/10 ,  H01L23/14 ,  H01L23/498

    Abstract: An apparatus including an electrostatic discharge circuit including a first circuit portion coupled beneath a die contact pad of an integrated circuit die and a second circuit portion in an interposer separate from the integrated circuit die, the interposer including a first contact point coupled to the contact pad of the integrated circuit die and a second contact point operable for connection to an external source. A method including forming an integrated circuit die including a first electrostatic discharge structure beneath a contact pad of the die; and coupling the die to an interposer including an interposer contact and a second electrostatic discharge structure, wherein a signal at the contact pad of the die is operable to be routed through the interposer.

Patent Agency Ranking