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公开(公告)号：US12139397B2
公开(公告)日：2024-11-12
申请号：US17028552
申请日：2020-09-22
Applicant: INVENSENSE, INC.
Inventor： Daesung Lee , Alan Cuthbertson
Abstract: Selective self-assembled monolayer patterning with sacrificial layer for devices is provided herein. A sensor device can include a handle layer and a device layer that comprises a first side and a second side. First portions of the first side are operatively connected to defined portions of the handle layer. At least one area of the second side comprises an anti-stiction area formed with an anti-stiction coating. The device can also include a Complementary Metal-Oxide-Semiconductor (CMOS) wafer operatively connected to second portions of the second side of the device layer. The CMOS wafer comprises at least one bump stop. The anti-stiction area faces the at least one bump stop.
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公开(公告)号：US20230037849A1
公开(公告)日：2023-02-09
申请号：US17877089
申请日：2022-07-29
Applicant: InvenSense, Inc.
Inventor： Daesung Lee , Alan Cuthbertson
IPC: B81C1/00
Abstract: A method includes forming a bumpstop from a first intermetal dielectric (IMD) layer and forming a via within the first IMD, wherein the first IMD is disposed over a first polysilicon layer, and wherein the first polysilicon layer is disposed over another IMD layer that is disposed over a substrate. The method further includes depositing a second polysilicon layer over the bumpstop and further over the via to connect to the first polysilicon layer. A standoff is formed over a first portion of the second polysilicon layer, and wherein a second portion of the second polysilicon layer is exposed. The method includes depositing a bond layer over the standoff.
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公开(公告)号：US11542154B2
公开(公告)日：2023-01-03
申请号：US17206079
申请日：2021-03-18
Applicant: InvenSense, Inc.
Inventor： Ashfaque Uddin , Daesung Lee , Alan Cuthbertson
Abstract: A method includes fusion bonding a handle wafer to a first side of a device wafer. The method further includes depositing a first mask on a second side of the device wafer, wherein the second side is planar. A plurality of dimple features is formed on an exposed portion on the second side of the device wafer. The first mask is removed from the second side of the device wafer. A second mask is deposited on the second side of the device wafer that corresponds to a standoff. An exposed portion on the second side of the device wafer is etched to form the standoff. The second mask is removed. A rough polysilicon layer is deposited on the second side of the device wafer. A eutectic bond layer is deposited on the standoff. In some embodiments, a micro-electro-mechanical system (MEMS) device pattern is etched into the device wafer.
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公开(公告)号：US11267699B2
公开(公告)日：2022-03-08
申请号：US16796310
申请日：2020-02-20
Applicant: INVENSENSE, INC.
Inventor： Alan Cuthbertson , Daesung Lee
Abstract: A modification to rough polysilicon using ion implantation and silicide is provided herein. A method can comprise depositing a hard mask on a single crystal silicon, patterning the hard mask, and depositing metal on the single crystal silicon. The method also can comprise forming silicide based on causing the metal to react with exposed silicon of the single crystal silicon. Further, the method can comprise removing unreacted metal and stripping the hard mask from the single crystal silicon. Another method comprises forming a MEMS layer, wherein the forming comprises fusion bonding a handle layer with a device layer. The method also can comprise implanting rough polysilicon on the device layer. Implanting the rough polysilicon can comprise performing ion implantation of the rough polysilicon. Further, the method can comprise performing high temperature annealing. The high temperature can comprise a temperature in a range between around 700 and 1100 degrees Celsius.
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公开(公告)号：US10906802B2
公开(公告)日：2021-02-02
申请号：US16440816
申请日：2019-06-13
Applicant: InvenSense, Inc.
Inventor： Daesung Lee , Dongyang Kang , Chienlu Chang , Bongsang Kim , Alan Cuthbertson
Abstract: Provided herein is a method including fusion bonding a handle wafer to a first side of a device wafer. Standoffs are formed on a second side of the device wafer. A first hardmask is deposited on the second side. A second hardmask is deposited on the first hardmask. A surface of the second hardmask is planarized. A photoresist is deposited on the second hardmask, wherein the photoresist includes a MEMS device pattern. The MEMS device pattern is etched into the second hardmask. The MEMS device pattern is etched into the first hardmask, wherein the etching stops before reaching the device wafer. The photoresist and the second hardmask are removed. The MEMS device pattern is further etched into the first hardmask, wherein the further etching reaches the device wafer. The MEMS device pattern is etched into the device wafer. The first hardmask is removed.
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Patent Agency Ranking
公开(公告)号：US10773951B2
公开(公告)日：2020-09-15
申请号：US16366672
申请日：2019-03-27
Applicant: InvenSense, Inc.
Inventor： Daesung Lee , Jeff Chunchieh Huang
Abstract: An apparatus includes a MEMS wafer with a device layer and a handle substrate bonded to the device layer. The apparatus also includes a CMOS wafer including an oxide layer, and a passivation layer overlying the oxide layer. A bonding electrode overlies the passivation layer and a bump stop electrode overlies the passivation layer. A eutectic bond is between a first bonding metal on the bonding electrode and a second bonding metal on the MEMS wafer. A sensing electrode is positioned adjacent to the bump stop electrode and the bonding electrode. A sensing gap is positioned between the sensing electrode and the device layer, wherein the sensing gap is greater than a bump stop gap positioned between the bump stop electrode and the device layer.
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公开(公告)号：US20200270123A1
公开(公告)日：2020-08-27
申请号：US16796310
申请日：2020-02-20
Applicant: INVENSENSE, INC.
Inventor： Alan Cuthbertson , Daesung Lee
Abstract: A modification to rough polysilicon using ion implantation and silicide is provided herein. A method can comprise depositing a hard mask on a single crystal silicon, patterning the hard mask, and depositing metal on the single crystal silicon. The method also can comprise forming silicide based on causing the metal to react with exposed silicon of the single crystal silicon. Further, the method can comprise removing unreacted metal and stripping the hard mask from the single crystal silicon. Another method can comprise forming a MEMS layer based on fusion bonding a handle MEMS with a device layer. The method also can comprise implanting rough polysilicon on the device layer. Implanting the rough polysilicon can comprise performing ion implantation of the rough polysilicon. Further, the method can comprise performing high temperature annealing. The high temperature can comprise a temperature in a range between around 700 and 1100 degrees Celsius.
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公开(公告)号：US10035702B2
公开(公告)日：2018-07-31
申请号：US15356916
申请日：2016-11-21
Applicant: INVENSENSE, INC.
Inventor： Daesung Lee
CPC classification number: B81C1/00801 , B81B7/0025 , B81B2207/07 , B81C2201/053 , B81C2203/0785
Abstract: A method and system for preparing a semiconductor wafer are disclosed. In a first aspect, the method comprises providing a passivation layer over a patterned top metal on the semiconductor wafer, etching the passivation layer to open a bond pad in the semiconductor wafer using a first mask, depositing a protection layer on the semiconductor wafer, patterning the protective layer using a second mask, and etching the passivation layer to open other electrodes in the semiconductor wafer using a third mask. The system comprises a MEMS device that further comprises a first substrate and a second substrate bonded to the first substrate, wherein the second substrate is prepared by the aforementioned steps of the method.
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公开(公告)号：US20250145456A1
公开(公告)日：2025-05-08
申请号：US19016875
申请日：2025-01-10
Applicant: InvenSense, Inc.
Inventor： Daesung Lee , Alan Cuthbertson
Abstract: A method includes forming a bumpstop from a first intermetal dielectric (IMD) layer and forming a via within the first IMD, wherein the first IMD is disposed over a first polysilicon layer, and wherein the first polysilicon layer is disposed over another IMD layer that is disposed over a substrate. The method further includes depositing a second polysilicon layer over the bumpstop and further over the via to connect to the first polysilicon layer. A standoff is formed over a first portion of the second polysilicon layer, and wherein a second portion of the second polysilicon layer is exposed. The method includes depositing a bond layer over the standoff.
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公开(公告)号：US11919769B2
公开(公告)日：2024-03-05
申请号：US18071322
申请日：2022-11-29
Applicant: InvenSense, Inc.
Inventor： Ashfaque Uddin , Daesung Lee , Alan Cuthbertson
CPC classification number: B81C1/00238 , B81B7/008 , B81C2201/013 , B81C2203/035
Abstract: A method includes fusion bonding a handle wafer to a first side of a device wafer. The method further includes depositing a first mask on a second side of the device wafer, wherein the second side is planar. A plurality of dimple features is formed on an exposed portion on the second side of the device wafer. The first mask is removed from the second side of the device wafer. A second mask is deposited on the second side of the device wafer that corresponds to a standoff. An exposed portion on the second side of the device wafer is etched to form the standoff. The second mask is removed. A rough polysilicon layer is deposited on the second side of the device wafer. A eutectic bond layer is deposited on the standoff. In some embodiments, a micro-electro-mechanical system (MEMS) device pattern is etched into the device wafer.
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