公开(公告)号：US09633951B2

公开(公告)日：2017-04-25

申请号：US11595206

申请日：2006-11-10

Applicant: Mark Pavier ,  Andrew N. Sawle ,  Martin Standing

Inventor： Mark Pavier ,  Andrew N. Sawle ,  Martin Standing

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538 ,  H01L23/31 ,  H01L23/367 ,  H01L23/433 ,  H01L23/492 ,  H01L23/00 ,  H01L23/14

CPC classification number: H01L23/043 ,  H01L21/56 ,  H01L23/142 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/4334 ,  H01L23/492 ,  H01L23/49562 ,  H01L23/49582 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/37 ,  H01L24/83 ,  H01L24/97 ,  H01L25/07 ,  H01L2224/0346 ,  H01L2224/0508 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/33181 ,  H01L2224/37147 ,  H01L2224/73153 ,  H01L2224/73267 ,  H01L2224/83815 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0106 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/40252 ,  H01L2924/403 ,  H01L2924/40407 ,  H01L2224/82 ,  H01L2224/83

Abstract: A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.

公开(公告)号：US08552543B2

公开(公告)日：2013-10-08

申请号：US11983827

申请日：2007-11-13

Applicant: Mark Pavier

Inventor： Mark Pavier

IPC: H01L23/12

CPC classification number: H01L23/492 ,  H01L23/13 ,  H01L24/33 ,  H01L2224/32245 ,  H01L2224/73153 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/10158 ,  H01L2924/13055 ,  H01L2924/13091

Abstract: A semiconductor package that includes a conductive clip having an interior surface that includes a plurality of spaced raised portions, a semiconductor device having a first major surface that includes a plurality of spaced depressions each receiving one of the raised portions in the interior thereof, and a conductive adhesive disposed between each raised portion and a respective interior surface of a depression.

Abstract translation: 一种半导体封装件，其包括具有内表面的导电夹子，所述内部表面包括多个间隔开的凸起部分，半导体器件具有第一主表面，所述第一主表面包括多个间隔开的凹部，每个凹部均接纳其内部中的一个凸起部分， 导电粘合剂设置在每个凸起部分和凹陷的相应内表面之间。

公开(公告)号：US07923289B2

公开(公告)日：2011-04-12

申请号：US11731140

申请日：2007-03-30

Applicant: Mark Pavier ,  Andy Farlow

Inventor： Mark Pavier ,  Andy Farlow

IPC: H01L21/44

CPC classification number: H01L24/33 ,  B23K1/0006 ,  B23K1/0016 ,  B23K35/0244 ,  B23K35/025 ,  B23K2101/42 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/16 ,  H01L2224/29 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29188 ,  H01L2224/2929 ,  H01L2224/29311 ,  H01L2224/29313 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/29388 ,  H01L2224/32245 ,  H01L2224/325 ,  H01L2224/73153 ,  H01L2224/83232 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/157 ,  H01L2924/1579 ,  H01L2924/3011 ,  H01L2924/01083 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A process for fabricating a semiconductor package which includes using an exothermically active nanoparticle paste to join an electrode of a semiconductor die to a support body.

Abstract translation: 一种制造半导体封装的方法，其包括使用放热活性纳米粒子糊将半导体管芯的电极连接到支撑体。

公开(公告)号：US20090218684A1

公开(公告)日：2009-09-03

申请号：US12359735

申请日：2009-01-26

Applicant: Mark Pavier ,  Danish Khatri ,  Daniel Cutler ,  Andrew Neil Sawle ,  Susan Johns ,  Martin Carroll ,  David Paul Jones

Inventor： Mark Pavier ,  Danish Khatri ,  Daniel Cutler ,  Andrew Neil Sawle ,  Susan Johns ,  Martin Carroll ,  David Paul Jones

IPC: H01L23/498

CPC classification number: H01L23/492 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05599 ,  H01L2224/05639 ,  H01L2224/13007 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/32245 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A power semiconductor package that includes a power semiconductor device having a threshold voltage that does not vary when subjected to an autoclave test.

Abstract translation: 一种功率半导体封装，其包括具有阈值电压的功率半导体器件，所述阈值电压在进行高压釜测试时不变化。

公开(公告)号：US07402507B2

公开(公告)日：2008-07-22

申请号：US11367725

申请日：2006-03-03

Applicant: Martin Standing ,  Mark Pavier ,  Robert J. Clarke ,  Andrew Sawle ,  Kenneth McCartney

Inventor： Martin Standing ,  Mark Pavier ,  Robert J. Clarke ,  Andrew Sawle ,  Kenneth McCartney

IPC: H01L21/20

CPC classification number: H01L21/4825 ,  H01L21/4867 ,  H01L23/544 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/27 ,  H01L24/29 ,  H01L24/33 ,  H01L24/40 ,  H01L24/743 ,  H01L24/83 ,  H01L25/16 ,  H01L25/50 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/743 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/0266 ,  H05K3/1241 ,  H05K3/245 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/29099

Abstract: A semiconductor package fabrication method in which drop on demand deposition of a drop on demand depositable material is used to prepare one component or a plurality of components of a semiconductor package or multi-chip module.

Abstract translation: 一种半导体封装制造方法，其中使用按需存放材料的按需投入沉积来制备半导体封装或多芯片模块的一个组件或多个组件。

公开(公告)号：US07345563B2

公开(公告)日：2008-03-18

申请号：US11375483

申请日：2006-03-14

Applicant: Mark Pavier

Inventor： Mark Pavier

IPC: H01F5/00

CPC classification number: H05K1/165 ,  H01F17/0006 ,  H01F17/043 ,  H01L23/645 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15192 ,  H05K3/429 ,  H05K2201/086 ,  H05K2201/09763 ,  H05K2203/0545

Abstract: An embedded inductor which includes a spiral conductive inductor embedded in a magnetically permeable body composed of particles of pre-sintered magnetically permeable (e.g. ferromagnetic) material and an epoxy binder.

Abstract translation: 一种嵌入式电感器，其包括嵌入由预烧结的导磁（例如铁磁）材料和环氧树脂粘合剂的颗粒组成的导磁体中的螺旋导电电感器。

公开(公告)号：US20070194441A1

公开(公告)日：2007-08-23

申请号：US11788584

申请日：2007-04-20

Applicant: Mark Pavier

Inventor： Mark Pavier

IPC: H01L23/043

CPC classification number: H01L24/97 ,  H01L23/04 ,  H01L23/24 ,  H01L24/83 ,  H01L2224/04105 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/73153 ,  H01L2224/73267 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15156 ,  H01L2924/16152 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor package has a thinned semiconductor die fixed in a shallow opening in a conductive body. The die electrodes at the bottom of the die are plated with a redistributed contact which overlaps the die bottom contact and an insulation body which fills the annular gap between the die and opening. A process is described for the manufacture of the package in which plural spaced openings in a lead frame body and are simultaneously processed and singulated at the end of the process.

公开(公告)号：US20060237825A1

公开(公告)日：2006-10-26

申请号：US11410457

申请日：2006-04-24

Applicant: Mark Pavier ,  Norman Connah

Inventor： Mark Pavier ,  Norman Connah

IPC: H01L23/495

CPC classification number: H01L23/49527 ,  H01L23/15 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/492 ,  H01L23/4951 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49844 ,  H01L23/49861 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/0603 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48644 ,  H01L2224/48744 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73255 ,  H01L2224/85207 ,  H01L2224/85444 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30107 ,  H03K17/567 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device package includes a die pad, a substrate disposed on the die pad, and a III-nitride based semiconductor device disposed on the substrate. The device package may also include a second semiconductor device disposed on the die pad or the substrate, which device may be electrically connected to the III-nitride based device to form a circuit.

公开(公告)号：US20060205112A1

公开(公告)日：2006-09-14

申请号：US11367725

申请日：2006-03-03

Applicant: Martin Standing ,  Mark Pavier ,  Robert Clarke ,  Andrew Sawle ,  Kenneth McCartney

Inventor： Martin Standing ,  Mark Pavier ,  Robert Clarke ,  Andrew Sawle ,  Kenneth McCartney

IPC: H01L21/00

CPC classification number: H01L21/4825 ,  H01L21/4867 ,  H01L23/544 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/27 ,  H01L24/29 ,  H01L24/33 ,  H01L24/40 ,  H01L24/743 ,  H01L24/83 ,  H01L25/16 ,  H01L25/50 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/743 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/0266 ,  H05K3/1241 ,  H05K3/245 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/29099

Abstract: A semiconductor package fabrication method in which drop on demand deposition of a drop on demand depositable material is used to prepare one component or a plurality of components of a semiconductor package or multi-chip module.

Abstract translation: 一种半导体封装制造方法，其中使用按需存放材料的按需投入沉积来制备半导体封装或多芯片模块的一个组件或多个组件。

公开(公告)号：US06891739B2

公开(公告)日：2005-05-10

申请号：US10090281

申请日：2002-03-04

Applicant: Bruno C. Nadd ,  David C. Tam ,  Mark Pavier ,  Glyn Connah

Inventor： Bruno C. Nadd ,  David C. Tam ,  Mark Pavier ,  Glyn Connah

IPC: H02P7/29 ,  H02M1/00 ,  H02M7/00 ,  H02P29/02

CPC classification number: H02P29/02 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2924/13055 ,  H01L2924/13091 ,  H02M1/32 ,  H02M1/36 ,  H02M1/38 ,  H02M7/003 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A fully protected H-bridge for a d-c motor consists of two high side MOSFETs and a control and logic IC on a first conductive heat sink all within a first package and two discrete low side MOSFETs. The entire bridge is controlled by the IC. Shoot thru protection is provided for each leg, and a PMW soft start sequence is provided through the control of the low side MOSFETs, programed by an external, chargeable RC circuit. Input signals to the high side MOSFETs select the operation modes. Protective circuits are provided for short circuit current and over current conditions. Sleep mode and braking/non braking control is also provided.

Abstract translation: 用于d-c电机的完全受保护的H桥由两个高边MOSFET组成，第一导电散热器上的控制和逻辑IC都在第一封装和两个分立的低侧MOSFET内。 整个桥梁由IC控制。 为每条支路提供射击保护，通过控制低端MOSFET提供PMW软起动序列，由外部可充电RC电路编程。 输入高边MOSFET的信号选择工作模式。 为短路电流和过流条件提供保护电路。 还提供睡眠模式和制动/非制动控制。