公开(公告)号：US4560962A

公开(公告)日：1985-12-24

申请号：US527840

申请日：1983-08-30

Applicant: Michael Barrow

Inventor： Michael Barrow

IPC: H01P3/08 ,  H05K1/00 ,  H05K1/02 ,  H05K3/42 ,  H05K3/46 ,  H01P5/12

CPC classification number: H01P3/081 ,  H01P3/088 ,  H05K1/024 ,  H05K1/025 ,  H05K3/46 ,  H05K1/0289 ,  H05K1/0298 ,  H05K2201/0191 ,  H05K2201/09309 ,  H05K2201/09327 ,  H05K2201/09609 ,  H05K3/429

Abstract: A printed circuit board of six planar layers has the layers separated by a dielectric of epoxy glass. The two central layer planes form a ground plane and a voltage plane. The two external planes and the internal planes involve series of microstrip signal lines of specially calculated widths and dielectric separations to provide an essentially 100 ohm characteristic impedance for the signal lines in reference to the ground and voltage planes.

Abstract translation: 六个平面层的印刷电路板具有由环氧玻璃的电介质隔开的层。 两个中心层平面形成接地平面和电压平面。 两个外部平面和内部平面涉及特定计算宽度和介质分离的一系列微带信号线，以便为参考地面和电压平面的信号线提供基本上100欧姆的特征阻抗。

公开(公告)号：US08207022B1

公开(公告)日：2012-06-26

申请号：US12931326

申请日：2011-01-27

Applicant: Robert Francis Darveaux ,  Michael Barrow ,  Miguel Angel Jimarez ,  Jae Dong Kim ,  Dae Keun Park ,  Ki Wook Lee ,  Ju Hoon Yoon

Inventor： Robert Francis Darveaux ,  Michael Barrow ,  Miguel Angel Jimarez ,  Jae Dong Kim ,  Dae Keun Park ,  Ki Wook Lee ,  Ju Hoon Yoon

IPC: B29C31/00 ,  H01L23/29

CPC classification number: H01L23/28 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105

Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

Abstract translation: 曝光的芯片包覆成型的倒装芯片封装包括衬底。 芯片安装在基板的上表面上。 该包装还包括填充模具的活性表面和基材的上表面之间的空间的模具盖。 模具帽包括主表面，从基板的上表面延伸到主表面的侧壁，与模具的非活性表面共面并从模具的非活性表面的外围边缘向外延伸的环形表面，并且突出 表面在主表面和环形表面之间延伸。 模具盖不覆盖模具的非活性表面，使得从模具到周围环境的热传递最大化并且封装厚度最小化。

公开(公告)号：US06498390B1

公开(公告)日：2002-12-24

申请号：US09154258

申请日：1998-09-16

Applicant: Michael Barrow

Inventor： Michael Barrow

IPC: H01L23495

CPC classification number: H01L23/3128 ,  H01L23/36 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An integrated circuit package which may have a thermally conductive tape that attaches a thermal element to a package housing. The housing encloses an integrated circuit that is mounted to a substrate. The thermally conductive tape may be configured to conform with any warpage in the package and prevent the creation of air void in the housing/thermal element interface.

Abstract translation: 可以具有将热元件附接到封装壳体的导热带的集成电路封装。 外壳包含一个安装在基板上的集成电路。 导热带可以被配置成符合包装中的任何翘曲并且防止在壳体/热元件接口中产生空气空隙。

公开(公告)号：US06420651B1

公开(公告)日：2002-07-16

申请号：US09881447

申请日：2001-06-12

Applicant: Michael Barrow

Inventor： Michael Barrow

IPC: H01L2328

CPC classification number: H01L24/06 ,  H01L21/565 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/06179 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49179 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An integrated circuit package which has an integrated circuit mounted to a substrate. The package includes a plurality of bond wires that couple bond pads of the integrated circuit to corresponding bond pads of the substrate. The bond wires may have an essentially uniform bond wire density about an entire outer perimeter of the integrated circuit including the corners of the circuit. The integrated circuit and bond wires are enclosed by an injected molded plastic housing. It is believed that the bond wires located at the corners impede the flow of the injected plastic and reduce the amount of wire sweep in the package from packages in the prior art. Additionally, the essentially uniform bond wire density may create a uniform fluidic resistance to the injected plastic. The uniform resistance also reduces the amount of wire sweep from packages in the prior art. The bond wires located at the corners may be dummy wires that are not electrically connected to the integrated circuit.

Abstract translation: 一种集成电路封装，其具有安装到基板的集成电路。 封装包括将集成电路的焊盘耦合到衬底的相应接合焊盘的多个接合线。 接合线可以围绕包括电路的拐角的集成电路的整个外周边具有基本均匀的接合线密度。 集成电路和接合线被注入的模制塑料外壳封闭。 据信，位于角落处的接合线阻止注入的塑料的流动并且减少了现有技术中的封装中的封装中的电线扫描量。 另外，基本上均匀的粘合线密度可以产生对注入的塑料的均匀的流体阻力。 均匀的电阻也减少了现有技术中的封装线的扫线量。 位于拐角处的接合线可以是不与集成电路电连接的虚拟线。

公开(公告)号：US06110762A

公开(公告)日：2000-08-29

申请号：US225416

申请日：1999-01-05

Applicant: Michael Barrow

Inventor： Michael Barrow

IPC: H01L23/367 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/10 ,  H01L23/34

CPC classification number: H01L23/3672 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3011

Abstract: An integrated circuit package. The package includes a substrate which has a first surface, a second opposite surface and four corners. Each corner has a conductive plane and at least one via. The vias connect the conductive planes of the first surface with corresponding conductive planes located on the second surface of the substrate. An integrated circuit is mounted to the first surface of the substrate and enclosed by plastic. Solder balls are attached to the conductive planes and a number of individual solder pads located on the second surface of the package. The contacts are connected to a printed circuit board. A lid is attached to the conductive planes at the four corners of the substrate. Some of the heat generated by the integrated circuit conducts through the substrate and into the printed circuit board. Some of the heat within the substrate conducts into the lid through the conductive planes located at the corners of the package. The present invention thus provides two thermal paths, the printed circuit board and the lid, from the substrate of a plastic integrated circuit package.

Abstract translation: 集成电路封装。 该包装包括具有第一表面，第二相对表面和四个角的基底。 每个拐角都有一个导电平面和至少一个通孔。 通孔将第一表面的导电平面与位于基板的第二表面上的相应的导电平面连接。 集成电路安装到基板的第一表面并用塑料封装。 焊球附接到导电平面和位于封装的第二表面上的多个单独焊盘。 触点连接到印刷电路板。 在基板的四个角部处的导电平面上附接有盖。 由集成电路产生的一些热量通过衬底传导到印刷电路板中。 衬底内的一些热量通过位于封装角部的导电平面导入盖子。 因此，本发明从塑料集成电路封装的基板提供两个热路径，印刷电路板和盖。

公开(公告)号：US5875102A

公开(公告)日：1999-02-23

申请号：US832482

申请日：1997-04-02

Applicant: Michael Barrow

Inventor： Michael Barrow

IPC: B23K1/00 ,  B23K11/11 ,  H01L23/31 ,  H01L23/498 ,  H05K1/11 ,  H05K3/00 ,  H05K3/34 ,  H01L25/00 ,  H05K7/02

CPC classification number: H01L23/3128 ,  B23K1/0016 ,  B23K11/11 ,  H01L23/49816 ,  H01L23/49827 ,  H05K1/113 ,  H05K3/0094 ,  H01L2224/48235 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/114 ,  H05K2201/0959 ,  H05K2201/10666 ,  H05K2201/10734 ,  H05K2203/041 ,  H05K2203/1178 ,  H05K2203/1394 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/3478

Abstract: A ball grid array (BGA) integrated circuit package which has a plurality of vias connected to a plurality of solder pads located on a bottom surface of a package substrate. Each via has a portion located within a solder pad to increase the routing space of the substrate, and a portion located outside the solder pad to allow outgassing from the via. The bottom surface also has a solder mask which covers the vias and contains a number of holes that expose the solder pads. The holes allow solder balls to be attached to the solder pads. The solder balls can be reflowed to attach the package to a printed circuit board.

Abstract translation: 一种球栅阵列（BGA）集成电路封装，其具有连接到位于封装衬底的底表面上的多个焊盘的多个通孔。 每个通孔具有位于焊盘内的部分，以增加基板的布线空间，以及位于焊盘外部的部分，以允许从通孔脱气。 底表面还具有覆盖通孔的焊接掩模，并且包含许多露出焊盘的孔。 这些孔允许焊球附着在焊盘上。 可以回流焊球以将封装附接到印刷电路板。

公开(公告)号：US5796589A

公开(公告)日：1998-08-18

申请号：US575917

申请日：1995-12-20

Applicant: Michael Barrow

Inventor： Michael Barrow

IPC: B23K1/00 ,  B23K11/11 ,  H01L23/31 ,  H01L23/498 ,  H05K1/11 ,  H05K3/00 ,  H05K3/34 ,  H01R9/09 ,  H01L23/48 ,  H05K7/02

CPC classification number: H05K3/0094 ,  B23K1/0016 ,  B23K11/11 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H05K3/3436 ,  B23K2201/40 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/113 ,  H05K1/114 ,  H05K2201/0959 ,  H05K2201/10666 ,  H05K2201/10734 ,  H05K2203/041 ,  H05K2203/1178 ,  H05K2203/1394 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/3478 ,  Y02P70/613

Abstract: A ball grid array (BGA) integrated circuit package which has a plurality of vias located within the solder pads of a package substrate. The substrate supports an integrated circuit which is connected to the solder pads by the vias. Solder balls used to solder the package to an external printed circuit board are attached to the solder pads of the substrate. A solder mask plug is formed within the vias to prevent the solder balls from wicking into the vias. Locating the vias within the solder pads optimizes the routing space of the substrate and increases the routing density of the package.

Abstract translation: 一种球栅阵列（BGA）集成电路封装，其具有位于封装衬底的焊盘内的多个通孔。 衬底支持集成电路，其通过通孔连接到焊盘。 用于将封装焊接到外部印刷电路板的焊球附着到基板的焊盘上。 在通孔内形成焊接屏蔽塞，以防止焊球进入通孔。 在焊盘内定位通孔可优化衬底的布线空间，并增加封装的布线密度。

公开(公告)号：US4553111A

公开(公告)日：1985-11-12

申请号：US527841

申请日：1983-08-30

Applicant: Michael Barrow

Inventor： Michael Barrow

IPC: H01P3/08 ,  H05K1/00 ,  H05K1/02 ,  H05K3/42 ,  H05K3/46 ,  H01P5/00

CPC classification number: H01P3/081 ,  H01P3/088 ,  H05K1/025 ,  H05K3/46 ,  H05K1/0289 ,  H05K1/0298 ,  H05K2201/0191 ,  H05K2201/09309 ,  H05K2201/09327 ,  H05K2201/09609 ,  H05K3/429

Abstract: A multilayer printed circuit board for TTL logic components provides an approximate 100 ohm characteristic impedance between external microstrip signal lines and internal ground and voltage planes. The addition of two internal microstrip signal plane lines permits a much greater interconnectability capability and also saves a large percentage of spatial area for component mounting while still maintaining the 100 ohm impedance characteristic.

Abstract translation: 用于TTL逻辑元件的多层印刷电路板在外部微带线信号线和内部接地和电压平面之间提供约100欧姆的特性阻抗。 添加两个内部微带信号平面线允许更大的互连能力，并且还可以节省用于部件安装的大部分空间面积，同时仍然保持100欧姆的阻抗特性。

公开(公告)号：US20080064138A1

公开(公告)日：2008-03-13

申请号：US11926540

申请日：2007-10-29

Applicant: Michael Barrow

Inventor： Michael Barrow

IPC: H01L21/60

CPC classification number: H01L23/50 ,  H01L21/4853 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K3/3436 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49222 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2924/00012

Abstract: A ball grid array (BGA) integrated circuit package which has an outer two-dimensional array of solder balls and a center two-dimensional array of solder balls located on a bottom surface of a package substrate. The solder balls are typically reflowed to mount the package to a printed circuit board. Mounted to an opposite surface of the substrate is an integrated circuit that is electrically coupled to the solder balls by internal routing within the package. The outer array of solder balls are located the dimensional profile of the integrated circuit to reduce solder stresses induced by the differential thermal expansion between the integrated circuit and the substrate. The center solder balls are typically routed directly to ground and power pads of the package to provide a direct thermal and electrical path from the integrated circuit to the printed circuit board.

Abstract translation: 一种球栅阵列（BGA）集成电路封装，其具有焊盘的外部二维阵列和位于封装衬底的底表面上的焊球的中心二维阵列。 焊球通常被回流以将封装安装到印刷电路板上。 安装到基板的相对表面的是通过封装内的内部布线电耦合到焊球的集成电路。 焊球的外部阵列位于集成电路的尺寸轮廓上，以减少由集成电路和衬底之间的差分热膨胀引起的焊料应力。 中心焊球通常直接路由到封装的地和电源焊盘，以提供从集成电路到印刷电路板的直接热和电路径。

公开(公告)号：US20060069561A1

公开(公告)日：2006-03-30

申请号：US10938746

申请日：2004-09-10

Applicant: Valerie Beattie ,  Marilyn Adams ,  Michael Barrow

Inventor： Valerie Beattie ,  Marilyn Adams ,  Michael Barrow

IPC: G10L15/04

CPC classification number: G10L15/22 ,  G09B5/04 ,  G10L2015/225

Abstract: Methods and related computer program products, systems, and devices for providing intelligent feedback to a user based on audio input associated with a user reading a passage are disclosed. The method can include assessing a level of fluency of a user's reading of the sequence of words using speech recognition technology to compare the audio input with an expected sequence of words and providing feedback to the user related to the level of fluency for a word.

Abstract translation: 公开了用于基于与读取通道的用户相关联的音频输入向用户提供智能反馈的方法和相关的计算机程序产品，系统和设备。 该方法可以包括使用语音识别技术来评估用户对单词序列的读取的流畅程度，以将音频输入与预期的单词序列进行比较，并向用户提供与单词的流畅程度相关的反馈。