中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

33 records (took 0.014 seconds)

    Quad flat pack integrated circuit package
    4.
    发明授权
    Quad flat pack integrated circuit package 有权
    四路扁平封装集成电路封装

    公开(公告)号：US5949651A

    公开(公告)日：1999-09-07

    申请号：US179016

    申请日：1998-10-26

    Applicant: Michael Barrow

    Inventor： Michael Barrow

    IPC: H01L23/495 ,  H01L25/10 ,  H05K1/02 ,  H05K1/18

    CPC classification number: H05K1/181 ,  H01L23/49568 ,  H01L25/105 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/181 ,  H05K1/0203 ,  H05K2201/10446 ,  H05K2201/10545 ,  H05K2201/10689 ,  Y02P70/611

    Abstract: A quad flat pack (QFP) integrated circuit package that is modified to include a tab that increases the thermal efficiency of the package. The package contains an integrated circuit that is mounted to a die paddle of a lead frame. A plurality of leads extend from a first side of the die paddle. Placing all of the leads on one side of the package minimizes the difference in signal length between the leads. The tab extends from a second side of the die paddle. Both the leads and the tab extend from a plastic housing which encapsulates the integrated circuit. The tab provides a large conductive area which increases the heat transfer rate from the integrated circuit to the ambient, or an external thermal element.

    Abstract translation: 一种四平面封装（QFP）集成电路封装，经修改，包括一个提升封装热效率的接头。 该封装包含一个集成电路，该电路安装在引线框架的裸片上。 多个引线从芯片的第一侧延伸。 将封装的一侧放置所有引线可以最大限度地减少引线之间信号长度的差异。 突片从模片桨的第二侧延伸。 引线和突片均从封装集成电路的塑料外壳延伸。 该突片提供了大的导电区域，其增加了从集成电路到环境的热传递速率或外部热元件。

    Silicon metal-pillar conductors under stagger bond pads
    5.
    发明授权
    Silicon metal-pillar conductors under stagger bond pads 失效
    硅金属柱导体处于错位接合垫下

    公开(公告)号：US5880529A

    公开(公告)日：1999-03-09

    申请号：US734773

    申请日：1996-10-22

    Applicant: Michael Barrow

    Inventor： Michael Barrow

    IPC: H01L23/485 ,  H01L23/48

    CPC classification number: H01L24/05 ,  H01L24/06 ,  H01L2224/05552 ,  H01L2224/05599 ,  H01L2224/4943 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14

    Abstract: A bond pad layout for an integrated circuit die. The die includes a plurality of inner bond pads and a plurality of outer bond pads. To minimize the spacing pitch of the bond pads the die contains an inner layer of metallization that routes the outer bond pads to the inner portion of the integrated circuit. To enhance the structural integrity of the integrated circuit the die contains a plurality of dielectric pillars that support the bond pads. The inner layer of metallization is typically routed around the dielectric pillars so that the metallization does not create stress points in the die.

    Abstract translation: 集成电路管芯的焊盘布局。 芯片包括多个内部接合焊盘和多个外部接合焊盘。 为了最小化接合焊盘的间距，芯片包含将外部焊盘焊接到集成电路的内部的内部金属化层。 为了增强集成电路的结构完整性，芯片包含多个支撑接合焊盘的介电柱。 金属化的内层通常围绕介电柱布置，使得金属化不会在管芯中产生应力点。

    Variable pitch stagger die for optimal density
    6.
    发明授权
    Variable pitch stagger die for optimal density 失效
    可变螺距交错模具，用于最佳密度

    公开(公告)号：US5801450A

    公开(公告)日：1998-09-01

    申请号：US733518

    申请日：1996-10-18

    Applicant: Michael Barrow

    Inventor： Michael Barrow

    IPC: H01L23/485 ,  H01L23/498 ,  H01L23/48

    CPC classification number: H01L24/06 ,  H01L23/49838 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/06179 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49179 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/014 ,  H01L2924/14

    Abstract: A bond pad layout for an integrated circuit die. The integrated circuit has four opposing sides that intersect at four corners of the die. The top surface of the integrated circuit has a plurality of bond pads that extend along each side of the die. The bond pads are typically coupled to corresponding bond fingers of an integrated circuit package by bond wires. The spacing pitch of the bond pads in the center portions of the die are smaller than the bond pad pitch at the corners of the die. The larger bond pad pitch at the corners of the die compensate for fanout of the bond wires. The smaller bond pad pitch in the center portions of the die optimizes the number of bond pads that can be formed on the integrated circuit. The bond pad layout thus optimizes the number of bond pads while compensating for the fanout of the bond wires.

    Abstract translation: 集成电路管芯的焊盘布局。 集成电路具有在模具的四个角处相交的四个相对侧。 集成电路的顶表面具有沿模具的每一侧延伸的多个接合焊盘。 接合焊盘通常通过接合线耦合到集成电路封装的对应的接合指状物。 芯片的中心部分的接合焊盘的间隔距离小于管芯角部处的接合焊盘间距。 模具角落处的较大的焊盘间距补偿了接合线的扇出。 管芯的中心部分中较小的焊盘间距优化了可在集成电路上形成的接合焊盘的数量。 因此，焊盘布局优化了接合焊盘的数量，同时补偿了接合线的扇出。

    Intelligent tutoring feedback
    7.
    发明授权
    Intelligent tutoring feedback 有权
    智能辅导反馈

    公开(公告)号：US08109765B2

    公开(公告)日：2012-02-07

    申请号：US10938746

    申请日：2004-09-10

    Applicant: Valerie L. Beattie ,  Marilyn Jager Adams ,  Michael Barrow

    Inventor： Valerie L. Beattie ,  Marilyn Jager Adams ,  Michael Barrow

    IPC: G09B19/00 ,  G09B19/04 ,  G09B5/00 ,  G10L15/00

    CPC classification number: G10L15/22 ,  G09B5/04 ,  G10L2015/225

    Abstract: Methods and related computer program products, systems, and devices for providing intelligent feedback to a user based on audio input associated with a user reading a passage are disclosed. The method can include assessing a level of fluency of a user's reading of the sequence of words using speech recognition technology to compare the audio input with an expected sequence of words and providing feedback to the user related to the level of fluency for a word.

    Abstract translation: 公开了用于基于与读取通道的用户相关联的音频输入向用户提供智能反馈的方法和相关的计算机程序产品，系统和设备。 该方法可以包括使用语音识别技术来评估用户对单词序列的读取的流畅程度，以将音频输入与预期的单词序列进行比较，并向用户提供与单词的流畅程度相关的反馈。

Patent Agency Ranking