-
公开(公告)号：US20190355423A1
公开(公告)日：2019-11-21
申请号：US16525804
申请日：2019-07-30
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Silvia Beltrami , Angelo Visconti
Abstract: Methods of operating a memory device include programming a page of a memory block of the memory device using a particular starting programming voltage, determining a programming voltage indicative of a programming efficiency of the page of the memory block during programming of the page of the memory block, storing a representation of the programming voltage indicative of the programming efficiency of the page of the memory block, setting a starting programming voltage for a different page of the memory block in response to the stored representation of the programming voltage indicative of the programming efficiency of the page of the memory block, and programming the different page of the memory block using its starting programming voltage.
-
公开(公告)号：US09454427B2
公开(公告)日：2016-09-27
申请号：US14855203
申请日：2015-09-15
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Aswin Thiruvengadam , Angelo Visconti , Mauro Bonanomi , Richard E. Fackenthal , William Melton
IPC: G11C29/00 , G06F11/10 , G06F11/16 , G06F11/07 , G06F3/06 , G11C7/10 , G11C13/00 , G11C16/10 , G11C19/00
CPC classification number: G06F11/1008 , G06F3/0619 , G06F3/064 , G06F3/0644 , G06F3/0673 , G06F3/0679 , G06F11/0751 , G06F11/1048 , G06F11/1666 , G11C7/1006 , G11C7/1012 , G11C13/0004 , G11C13/0069 , G11C16/10 , G11C19/00
Abstract: This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error.
Abstract translation: 本公开涉及通过将要编程的数据移动到存储器以避免硬错误而避免在写入时间期间的存储器中的硬错误。 在一个实现中，将数据编程到存储器阵列的方法包括获得与所选择的存储器单元相对应的错误数据，移位数据模式，使得所选存储器单元要存储的值与硬错误相关联的值匹配，以及 将移位的数据模式编程到存储器阵列，使得编程到所选择的存储器单元的值与与硬错误相关联的值匹配。
-
公开(公告)号：US20160004595A1
公开(公告)日：2016-01-07
申请号：US14855203
申请日：2015-09-15
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Aswin Thiruvengadam , Angelo Visconti , Mauro Bonanomi , Richard E. Fackenthal , William Melton
CPC classification number: G06F11/1008 , G06F3/0619 , G06F3/064 , G06F3/0644 , G06F3/0673 , G06F3/0679 , G06F11/0751 , G06F11/1048 , G06F11/1666 , G11C7/1006 , G11C7/1012 , G11C13/0004 , G11C13/0069 , G11C16/10 , G11C19/00
Abstract: This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error.
Abstract translation: 本公开涉及通过将要编程的数据移动到存储器以避免硬错误而避免在写入时间期间的存储器中的硬错误。 在一个实现中，将数据编程到存储器阵列的方法包括获得与所选择的存储器单元相对应的错误数据，移位数据模式，使得所选存储器单元要存储的值与硬错误相关联的值匹配，以及 将移位的数据模式编程到存储器阵列，使得编程到所选择的存储器单元的值与与硬错误相关联的值匹配。
-
公开(公告)号：US09176831B2
公开(公告)日：2015-11-03
申请号：US14612103
申请日：2015-02-02
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Aswin Thiruvengadam , Angelo Visconti , Mauro Bonanomi , Richard E. Fackenthal , William Melton
CPC classification number: G06F11/1008 , G06F3/0619 , G06F3/064 , G06F3/0644 , G06F3/0673 , G06F3/0679 , G06F11/0751 , G06F11/1048 , G06F11/1666 , G11C7/1006 , G11C7/1012 , G11C13/0004 , G11C13/0069 , G11C16/10 , G11C19/00
Abstract: This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error.
Abstract translation: 本公开涉及通过将要编程的数据移动到存储器以避免硬错误而避免在写入时间期间的存储器中的硬错误。 在一个实现中，将数据编程到存储器阵列的方法包括获得与所选择的存储器单元相对应的错误数据，移位数据模式，使得所选存储器单元要存储的值与硬错误相关联的值匹配，以及 将移位的数据模式编程到存储器阵列，使得编程到所选择的存储器单元的值与与硬错误相关联的值匹配。
-
25.发明申请READING MEMORY CELL HISTORY DURING PROGRAM OPERATION FOR ADAPTIVE PROGRAMMING 有权在自适应编程程序运行期间读取存储单元历史公开(公告)号：US20140321206A1
公开(公告)日：2014-10-30
申请号：US14325183
申请日：2014-07-07
Applicant: Micron Technology, Inc.
Inventor： Angelo Visconti , Mattia Robustelli , Silvia Beltrami , Laura Tatiana Czeppel , Massimo Ernesto Bertuccio
CPC classification number: G11C16/3495 , G11C16/0483 , G11C16/10 , G11C16/3459
Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a memory device.
Abstract translation: 本文公开的主题涉及存储器件，更具体地涉及写入存储器件的性能。
-
Patent Agency Ranking
26.发明授权Reading memory cell history during program operation for adaptive programming 有权在编程操作期间读取存储单元历史以进行自适应编程公开(公告)号：US08773907B2
公开(公告)日：2014-07-08
申请号：US13902402
申请日：2013-05-24
Applicant: Micron Technology, Inc.
Inventor： Angelo Visconti , Mattia Robustelli , Slivia Beltrami , Laura Tatiana Czeppel , Massimo Ernesto Bertuccio
CPC classification number: G11C16/3495 , G11C16/0483 , G11C16/10 , G11C16/3459
Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a memory device.
Abstract translation: 本文公开的主题涉及存储器件，更具体地涉及写入存储器件的性能。
-
公开(公告)号：US20240403177A1
公开(公告)日：2024-12-05
申请号：US18678557
申请日：2024-05-30
Applicant: Micron Technology, Inc.
Inventor： Su Wei Lim , Senthil Murugan Thangaraj , Marco Sforzin , Daniele Balluchi , Massimiliano Patriarca , Giorgio Servalli , Angelo Visconti , Antonino Capri’ , Garth N. Grubb , Amitava Majumdar , Miguel Mares
Abstract: Correctable error pattern information for a memory device can be based on data received from or using a data pin of the memory device. The memory device can include, for example, a DRAM device comprising an array of memory cells. Based on the error pattern information, firmware or software can be used to identify respective physical portions of the array comprising data with correctable errors. In an example, one or more fault locations in the memory device can be identified, the fault location corresponding to multiple cells in the array and comprising the data with correctable errors. In response to identifying the fault location in the array, one or more memory pages corresponding to the location(s) can be offlined or removed from an addressable memory space. In an example, the memory device comprises a portion of a compute express link (CXL) system.
-
公开(公告)号：US12094512B2
公开(公告)日：2024-09-17
申请号：US17896345
申请日：2022-08-26
Applicant: Micron Technology, Inc.
Inventor： Angelo Visconti , Andrea Locatelli
IPC: G11C11/22
CPC classification number: G11C11/2295 , G11C11/221 , G11C11/2259 , G11C11/2273 , G11C11/2293 , G11C11/2297
Abstract: Systems and methods described herein may enable a memory system to selectively provide a signal boost to a memory cell in response to a change in operating condition, like a change in temperature. The systems and methods may include determining to generate a signal boost for a first duration of time and in response to determining to generate the signal boost, generating the signal boost causing an increase in voltage applied to a signal line coupled to a memory cell. The systems and methods may further include, after the first duration of time, ceasing generation of the signal boost.
-
公开(公告)号：US20240096390A1
公开(公告)日：2024-03-21
申请号：US18521872
申请日：2023-11-28
Applicant: Micron Technology, Inc.
Inventor： Angelo Visconti
IPC: G11C11/22
CPC classification number: G11C11/2297 , G11C11/221
Abstract: Methods, systems, and devices for switch and hold biasing for memory cell imprint recovery are described. A memory device may be configured to perform an imprint recovery procedure that includes applying one or more recovery pulses to memory cells, where each recovery pulse is associated with a voltage polarity and includes a first portion with a first voltage magnitude and a second portion with a second voltage magnitude that is lower than the first voltage magnitude. In some examples, the first voltage magnitude may correspond to a voltage that imposes a saturation polarization on a memory cell (e.g., on a ferroelectric capacitor, a polarization corresponding to the associated voltage polarity) and the second voltage magnitude may correspond to a voltage magnitude that is high enough to maintain the saturation polarization (e.g., to prevent a reduction of polarization) of the memory cell.
-
公开(公告)号：US11908506B2
公开(公告)日：2024-02-20
申请号：US17196661
申请日：2021-03-09
Applicant: Micron Technology, Inc.
Inventor： Angelo Visconti , Giorgio Servalli , Andrea Locatelli
CPC classification number: G11C11/2259 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G11C11/221 , G11C11/2255 , G11C11/2257 , G11C11/2273 , G11C11/2275
Abstract: Methods, systems, and devices for memory cell biasing techniques are described. A memory cell may be accessed during an access phase of an access operation. A pre-charge phase of the access phase may be initiated. The memory cell may be biased to a voltage (e.g., a non-zero voltage) after the pre-charge phase. In some examples, the memory cell may be biased to the voltage when a word line is unbiased and the memory cell is isolated from the digit line.
-
-
-
-
-
-
-
-
-
Search Results
79
records
(took 0.018 seconds)
